📄 alarm_new.rpt
字号:
-- Node name is '~277~6'
-- Equation name is '~277~6', location is LC7_A23, type is buried.
-- synthesized logic cell
_LC7_A23 = LCELL( _EQ039);
_EQ039 = _LC7_A18
# _LC5_A18
# _LC6_A23
# _LC3_A23;
-- Node name is ':298'
-- Equation name is '_LC4_B16', type is buried
!_LC4_B16 = _LC4_B16~NOT;
_LC4_B16~NOT = LCELL( _EQ040);
_EQ040 = !_LC2_B16 & !sec2 & !sec3 & !sec4;
-- Node name is '~329~1'
-- Equation name is '~329~1', location is LC2_B14, type is buried.
-- synthesized logic cell
_LC2_B14 = LCELL( _EQ041);
_EQ041 = !sec6 & !sec7;
-- Node name is '~329~2'
-- Equation name is '~329~2', location is LC1_A24, type is buried.
-- synthesized logic cell
_LC1_A24 = LCELL( _EQ042);
_EQ042 = hour5 & _LC4_A13 & _LC6_A24 & min0
# hour5 & _LC4_A13 & !_LC6_A24 & !min0
# !hour5 & !_LC4_A13 & _LC6_A24 & min0
# !hour5 & !_LC4_A13 & !_LC6_A24 & !min0;
-- Node name is '~329~3'
-- Equation name is '~329~3', location is LC2_A24, type is buried.
-- synthesized logic cell
_LC2_A24 = LCELL( _EQ043);
_EQ043 = !disp_mode1 & hour0 & _LC2_B14 & _LC4_A24
# !disp_mode1 & !hour0 & _LC2_B14 & !_LC4_A24;
-- Node name is '~329~4'
-- Equation name is '~329~4', location is LC3_A4, type is buried.
-- synthesized logic cell
_LC3_A4 = LCELL( _EQ044);
_EQ044 = _LC1_A4 & _LC2_A4 & min1 & min2
# !_LC1_A4 & _LC2_A4 & min1 & !min2
# _LC1_A4 & !_LC2_A4 & !min1 & min2
# !_LC1_A4 & !_LC2_A4 & !min1 & !min2;
-- Node name is '~329~5'
-- Equation name is '~329~5', location is LC8_A13, type is buried.
-- synthesized logic cell
_LC8_A13 = LCELL( _EQ045);
_EQ045 = hour3 & hour7 & _LC1_A16 & _LC2_A13
# hour3 & !hour7 & _LC1_A16 & !_LC2_A13
# !hour3 & hour7 & !_LC1_A16 & _LC2_A13
# !hour3 & !hour7 & !_LC1_A16 & !_LC2_A13;
-- Node name is '~329~6'
-- Equation name is '~329~6', location is LC5_A13, type is buried.
-- synthesized logic cell
_LC5_A13 = LCELL( _EQ046);
_EQ046 = _LC3_A4 & !_LC4_B16 & _LC8_A13
# _LC3_A4 & _LC8_A13 & !sec5;
-- Node name is '~329~7'
-- Equation name is '~329~7', location is LC8_A24, type is buried.
-- synthesized logic cell
_LC8_A24 = LCELL( _EQ047);
_EQ047 = hour1 & _LC3_A16 & _LC7_A18 & min7
# !hour1 & !_LC3_A16 & _LC7_A18 & min7
# hour1 & _LC3_A16 & !_LC7_A18 & !min7
# !hour1 & !_LC3_A16 & !_LC7_A18 & !min7;
-- Node name is '~329~8'
-- Equation name is '~329~8', location is LC5_A24, type is buried.
-- synthesized logic cell
_LC5_A24 = LCELL( _EQ048);
_EQ048 = _LC1_A24 & _LC2_A24 & _LC5_A13 & _LC8_A24;
-- Node name is '~329~9'
-- Equation name is '~329~9', location is LC1_A14, type is buried.
-- synthesized logic cell
_LC1_A14 = LCELL( _EQ049);
_EQ049 = !disp_mode0 & _LC8_A4 & min3 & !set
# !disp_mode0 & !_LC8_A4 & !min3 & !set;
-- Node name is '~329~10'
-- Equation name is '~329~10', location is LC1_A23, type is buried.
-- synthesized logic cell
_LC1_A23 = LCELL( _EQ050);
_EQ050 = hour6 & _LC1_A13 & _LC5_A18 & min5
# hour6 & _LC1_A13 & !_LC5_A18 & !min5
# !hour6 & !_LC1_A13 & _LC5_A18 & min5
# !hour6 & !_LC1_A13 & !_LC5_A18 & !min5;
-- Node name is '~329~11'
-- Equation name is '~329~11', location is LC2_A23, type is buried.
-- synthesized logic cell
_LC2_A23 = LCELL( _EQ051);
_EQ051 = hour2 & hour4 & _LC2_A16 & _LC3_A13
# hour2 & !hour4 & _LC2_A16 & !_LC3_A13
# !hour2 & hour4 & !_LC2_A16 & _LC3_A13
# !hour2 & !hour4 & !_LC2_A16 & !_LC3_A13;
-- Node name is '~329~12'
-- Equation name is '~329~12', location is LC1_A19, type is buried.
-- synthesized logic cell
_LC1_A19 = LCELL( _EQ052);
_EQ052 = _LC1_A18 & _LC4_A18 & min4 & min6
# !_LC1_A18 & _LC4_A18 & min4 & !min6
# _LC1_A18 & !_LC4_A18 & !min4 & min6
# !_LC1_A18 & !_LC4_A18 & !min4 & !min6;
-- Node name is '~329~13'
-- Equation name is '~329~13', location is LC4_A23, type is buried.
-- synthesized logic cell
_LC4_A23 = LCELL( _EQ053);
_EQ053 = _LC1_A14 & _LC1_A19 & _LC1_A23 & _LC2_A23;
-- Node name is ':351'
-- Equation name is '_LC6_B14', type is buried
!_LC6_B14 = _LC6_B14~NOT;
_LC6_B14~NOT = LCELL( _EQ054);
_EQ054 = !sec6 & !sec7
# !_LC1_B16 & !sec5 & !sec7;
-- Node name is ':363'
-- Equation name is '_LC1_B16', type is buried
!_LC1_B16 = _LC1_B16~NOT;
_LC1_B16~NOT = LCELL( _EQ055);
_EQ055 = !sec4
# !sec2 & !sec3
# !_LC2_B16 & !sec3;
-- Node name is ':381'
-- Equation name is '_LC2_B16', type is buried
!_LC2_B16 = _LC2_B16~NOT;
_LC2_B16~NOT = LCELL( _EQ056);
_EQ056 = !sec0 & !sec1;
-- Node name is '~388~1'
-- Equation name is '~388~1', location is LC8_B14, type is buried.
-- synthesized logic cell
_LC8_B14 = LCELL( _EQ057);
_EQ057 = min0 & min3 & min4 & min6;
-- Node name is '~389~1'
-- Equation name is '~389~1', location is LC3_B14, type is buried.
-- synthesized logic cell
_LC3_B14 = LCELL( _EQ058);
_EQ058 = !min0 & !min3 & !min4 & !sec5;
-- Node name is '~389~2'
-- Equation name is '~389~2', location is LC4_B14, type is buried.
-- synthesized logic cell
_LC4_B14 = LCELL( _EQ059);
_EQ059 = _LC2_B14 & _LC3_B14 & !_LC4_B16 & !min6;
-- Node name is ':447'
-- Equation name is '_LC5_B20', type is buried
_LC5_B20 = DFFE( _EQ060, GLOBAL( clk_4Hz), VCC, VCC, VCC);
_EQ060 = sound0 & sound1;
-- Node name is '~455~1'
-- Equation name is '~455~1', location is LC5_B14, type is buried.
-- synthesized logic cell
_LC5_B14 = LCELL( _EQ061);
_EQ061 = clk_1KHz & !min1 & !min2 & !min7;
-- Node name is '~455~2'
-- Equation name is '~455~2', location is LC7_B14, type is buried.
-- synthesized logic cell
_LC7_B14 = LCELL( _EQ062);
_EQ062 = _LC5_B14 & !_LC5_B20 & !_LC6_B14 & !min5
# _LC5_B14 & _LC5_B20 & _LC6_B14 & !min5;
-- Node name is ':459'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = DFFE( _EQ063, GLOBAL( clk_4Hz), VCC, VCC, VCC);
_EQ063 = _LC4_B14 & _LC7_B14
# _LC6_B14 & _LC7_B14 & _LC8_B14;
-- Node name is ':461'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = LCELL( _EQ064);
_EQ064 = alarm1 & clk_4Hz
# _LC1_B14;
Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\alarm_new.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,148K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -