📄 alarm_new.rpt
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Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\alarm_new.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 06/10/2004 11:59:32
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
alarm_new
EPF10K10LC84-3 31 19 0 0 0 % 65 11 %
User Pins: 31 19 0
Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\alarm_new.rpt
** FILE HIERARCHY **
|lpm_add_sub:463|
|lpm_add_sub:463|addcore:adder|
|lpm_add_sub:463|altshift:result_ext_latency_ffs|
|lpm_add_sub:463|altshift:carry_ext_latency_ffs|
|lpm_add_sub:463|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:464|
|lpm_add_sub:464|addcore:adder|
|lpm_add_sub:464|altshift:result_ext_latency_ffs|
|lpm_add_sub:464|altshift:carry_ext_latency_ffs|
|lpm_add_sub:464|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:465|
|lpm_add_sub:465|addcore:adder|
|lpm_add_sub:465|altshift:result_ext_latency_ffs|
|lpm_add_sub:465|altshift:carry_ext_latency_ffs|
|lpm_add_sub:465|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:466|
|lpm_add_sub:466|addcore:adder|
|lpm_add_sub:466|altshift:result_ext_latency_ffs|
|lpm_add_sub:466|altshift:carry_ext_latency_ffs|
|lpm_add_sub:466|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:467|
|lpm_add_sub:467|addcore:adder|
|lpm_add_sub:467|altshift:result_ext_latency_ffs|
|lpm_add_sub:467|altshift:carry_ext_latency_ffs|
|lpm_add_sub:467|altshift:oflow_ext_latency_ffs|
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\alarm_new.rpt
alarm_new
***** Logic for device 'alarm_new' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\alarm_new.rpt
alarm_new
** ERROR SUMMARY **
Info: Chip 'alarm_new' in device 'EPF10K10LC84-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
d ^
i C
R R R s O
E E E p c s N
S S S V _ l e a G a F
E h h E a a E C m k t h N h h h _ ^
R o o R m m R C o _ _ m o D o m o o # D n
V u u V i i V I d 4 a i u I u i u u T O C
E r r E n n E N e H h n r N r n r r C N E
D 5 6 D 1 2 D T 1 z r 0 5 T 4 5 0 7 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | alarm2
^nCE | 14 72 | ahour4
#TDI | 15 71 | amin4
ahour3 | 16 70 | amin5
ahour2 | 17 69 | amin7
amin3 | 18 68 | GNDINT
amin0 | 19 67 | clk_1KHz
VCCINT | 20 66 | sec0
sec1 | 21 65 | ear
sec3 | 22 EPF10K10LC84-3 64 | sec6
sec4 | 23 63 | VCCINT
sec2 | 24 62 | ahour6
sec7 | 25 61 | RESERVED
GNDINT | 26 60 | ahour1
RESERVED | 27 59 | alarm
RESERVED | 28 58 | RESERVED
RESERVED | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | min6
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ s m h h m V G d s s V G a m h m a m h
C n e i o o i C N i e e C N h i o i m i o
C C t n u u n C D s t c C D o n u n i n u
I O 2 r r 1 I I p _ 5 I I u 7 r 4 n 3 r
N N 0 3 N N _ a N N r 2 6 1
T F T T m m T T 7
I o i
G d n
e
0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\alarm_new.rpt
alarm_new
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A4 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
A13 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
A14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A16 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
A18 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 2/22( 9%)
A19 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
A23 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 18/22( 81%)
A24 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 0/2 13/22( 59%)
B14 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 15/22( 68%)
B16 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
B20 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 44/53 ( 83%)
Total logic cells used: 65/576 ( 11%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.32/4 ( 83%)
Total fan-in: 216/2304 ( 9%)
Total input pins required: 31
Total input I/O cell registers required: 0
Total output pins required: 19
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 65
Total flipflops required: 21
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 30/ 576 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 8 0 0 0 0 0 0 0 0 0 8 1 0 8 0 8 2 0 0 0 8 8 51/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 3 0 0 0 3 0 0 0 0 14/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 8 0 0 0 0 0 0 0 0 0 8 9 0 11 0 8 2 3 0 0 8 8 65/0
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\alarm_new.rpt
alarm_new
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
67 - - B -- INPUT 0 0 0 1 clk_1KHz
2 - - - -- INPUT G 0 0 0 1 clk_4Hz
42 - - - -- INPUT 0 0 0 2 disp_mode0
3 - - - 12 INPUT 0 0 0 2 disp_mode1
37 - - - 09 INPUT 0 0 0 1 hour0
53 - - - 20 INPUT 0 0 0 1 hour1
49 - - - 16 INPUT 0 0 0 1 hour2
38 - - - 10 INPUT 0 0 0 1 hour3
81 - - - 22 INPUT 0 0 0 1 hour4
10 - - - 01 INPUT 0 0 0 1 hour5
9 - - - 02 INPUT 0 0 0 1 hour6
78 - - - 24 INPUT 0 0 0 1 hour7
84 - - - -- INPUT 0 0 0 3 min0
39 - - - 11 INPUT 0 0 0 2 min1
36 - - - 07 INPUT 0 0 0 2 min2
52 - - - 19 INPUT 0 0 0 3 min3
50 - - - 17 INPUT 0 0 0 3 min4
80 - - - 23 INPUT 0 0 0 2 min5
54 - - - 21 INPUT 0 0 0 3 min6
48 - - - 15 INPUT 0 0 0 2 min7
66 - - B -- INPUT 0 0 0 1 sec0
21 - - B -- INPUT 0 0 0 1 sec1
24 - - B -- INPUT 0 0 0 2 sec2
22 - - B -- INPUT 0 0 0 2 sec3
23 - - B -- INPUT 0 0 0 2 sec4
44 - - - -- INPUT 0 0 0 3 sec5
64 - - B -- INPUT 0 0 0 2 sec6
25 - - B -- INPUT 0 0 0 2 sec7
35 - - - 06 INPUT 0 0 0 1 set
1 - - - -- INPUT G 0 0 0 0 set_ahr
43 - - - -- INPUT G 0 0 0 0 set_amin
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
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