ecc.rpt

用verlog HDL写的电子日历,可以显示年,月,日和时间,具有闹铃的功能

Project Information               e:\amj\eda\experiment\calendar_clock\ecc.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 05/23/2005 22:25:16

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

ecc       EPF10K10LC84-3   4      22     0    0         0  %    400      69 %

User Pins:                 4      22     0  



Project Information               e:\amj\eda\experiment\calendar_clock\ecc.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Flipflop '|route:92|:120' stuck at GND
Warning: Flipflop '|fdiv_cnt:94|fdiv12:70|:102' stuck at GND
Warning: Flipflop '|fdiv_cnt:94|fdiv12:70|:101' stuck at GND
Warning: Flipflop '|fdiv_cnt:94|fdiv28_31:57|:499' stuck at GND
Warning: Flipflop '|fdiv_cnt:94|fdiv12:70|:100' stuck at GND


Project Information               e:\amj\eda\experiment\calendar_clock\ecc.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

ecc@53                            alarm
ecc@1                             clk
ecc@24                            dp
ecc@44                            mode
ecc@23                            out0
ecc@22                            out1
ecc@21                            out2
ecc@19                            out3
ecc@18                            out4
ecc@17                            out5
ecc@16                            out6
ecc@78                            scan_en1
ecc@79                            scan_en2
ecc@80                            scan_en3
ecc@81                            scan_en4
ecc@10                            scan_en5
ecc@11                            scan_en6
ecc@84                            select
ecc@83                            set


Project Information               e:\amj\eda\experiment\calendar_clock\ecc.rpt

** FILE HIERARCHY **



|p7segment:12|
|clkdiv1000:91|
|clkdiv1000:91|lpm_add_sub:62|
|clkdiv1000:91|lpm_add_sub:62|addcore:adder|
|clkdiv1000:91|lpm_add_sub:62|altshift:result_ext_latency_ffs|
|clkdiv1000:91|lpm_add_sub:62|altshift:carry_ext_latency_ffs|
|clkdiv1000:91|lpm_add_sub:62|altshift:oflow_ext_latency_ffs|
|route:92|
|route:92|lpm_add_sub:263|
|route:92|lpm_add_sub:263|addcore:adder|
|route:92|lpm_add_sub:263|altshift:result_ext_latency_ffs|
|route:92|lpm_add_sub:263|altshift:carry_ext_latency_ffs|
|route:92|lpm_add_sub:263|altshift:oflow_ext_latency_ffs|
|route:92|lpm_add_sub:264|
|route:92|lpm_add_sub:264|addcore:adder|
|route:92|lpm_add_sub:264|altshift:result_ext_latency_ffs|
|route:92|lpm_add_sub:264|altshift:carry_ext_latency_ffs|
|route:92|lpm_add_sub:264|altshift:oflow_ext_latency_ffs|
|route:92|lpm_add_sub:265|
|route:92|lpm_add_sub:265|addcore:adder|
|route:92|lpm_add_sub:265|altshift:result_ext_latency_ffs|
|route:92|lpm_add_sub:265|altshift:carry_ext_latency_ffs|
|route:92|lpm_add_sub:265|altshift:oflow_ext_latency_ffs|
|route:92|lpm_add_sub:266|
|route:92|lpm_add_sub:266|addcore:adder|
|route:92|lpm_add_sub:266|altshift:result_ext_latency_ffs|
|route:92|lpm_add_sub:266|altshift:carry_ext_latency_ffs|
|route:92|lpm_add_sub:266|altshift:oflow_ext_latency_ffs|
|fdiv_cnt:94|
|fdiv_cnt:94|fdiv60:53|
|fdiv_cnt:94|fdiv60:53|lpm_add_sub:96|
|fdiv_cnt:94|fdiv60:53|lpm_add_sub:96|addcore:adder|
|fdiv_cnt:94|fdiv60:53|lpm_add_sub:96|altshift:result_ext_latency_ffs|
|fdiv_cnt:94|fdiv60:53|lpm_add_sub:96|altshift:carry_ext_latency_ffs|
|fdiv_cnt:94|fdiv60:53|lpm_add_sub:96|altshift:oflow_ext_latency_ffs|
|fdiv_cnt:94|fdiv60:53|lpm_add_sub:97|
|fdiv_cnt:94|fdiv60:53|lpm_add_sub:97|addcore:adder|
|fdiv_cnt:94|fdiv60:53|lpm_add_sub:97|altshift:result_ext_latency_ffs|
|fdiv_cnt:94|fdiv60:53|lpm_add_sub:97|altshift:carry_ext_latency_ffs|
|fdiv_cnt:94|fdiv60:53|lpm_add_sub:97|altshift:oflow_ext_latency_ffs|
|fdiv_cnt:94|fdiv60:54|
|fdiv_cnt:94|fdiv60:54|lpm_add_sub:96|
|fdiv_cnt:94|fdiv60:54|lpm_add_sub:96|addcore:adder|
|fdiv_cnt:94|fdiv60:54|lpm_add_sub:96|altshift:result_ext_latency_ffs|
|fdiv_cnt:94|fdiv60:54|lpm_add_sub:96|altshift:carry_ext_latency_ffs|
|fdiv_cnt:94|fdiv60:54|lpm_add_sub:96|altshift:oflow_ext_latency_ffs|
|fdiv_cnt:94|fdiv60:54|lpm_add_sub:97|
|fdiv_cnt:94|fdiv60:54|lpm_add_sub:97|addcore:adder|
|fdiv_cnt:94|fdiv60:54|lpm_add_sub:97|altshift:result_ext_latency_ffs|
|fdiv_cnt:94|fdiv60:54|lpm_add_sub:97|altshift:carry_ext_latency_ffs|
|fdiv_cnt:94|fdiv60:54|lpm_add_sub:97|altshift:oflow_ext_latency_ffs|
|fdiv_cnt:94|fdiv24:55|
|fdiv_cnt:94|fdiv24:55|lpm_add_sub:96|
|fdiv_cnt:94|fdiv24:55|lpm_add_sub:96|addcore:adder|
|fdiv_cnt:94|fdiv24:55|lpm_add_sub:96|altshift:result_ext_latency_ffs|
|fdiv_cnt:94|fdiv24:55|lpm_add_sub:96|altshift:carry_ext_latency_ffs|
|fdiv_cnt:94|fdiv24:55|lpm_add_sub:96|altshift:oflow_ext_latency_ffs|
|fdiv_cnt:94|fdiv24:55|lpm_add_sub:97|
|fdiv_cnt:94|fdiv24:55|lpm_add_sub:97|addcore:adder|
|fdiv_cnt:94|fdiv24:55|lpm_add_sub:97|altshift:result_ext_latency_ffs|
|fdiv_cnt:94|fdiv24:55|lpm_add_sub:97|altshift:carry_ext_latency_ffs|
|fdiv_cnt:94|fdiv24:55|lpm_add_sub:97|altshift:oflow_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:554|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:554|addcore:adder|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:554|altshift:result_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:554|altshift:carry_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:554|altshift:oflow_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:555|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:555|addcore:adder|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:555|altshift:result_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:555|altshift:carry_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:555|altshift:oflow_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:556|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:556|addcore:adder|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:556|altshift:result_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:556|altshift:carry_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:556|altshift:oflow_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:557|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:557|addcore:adder|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:557|altshift:result_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:557|altshift:carry_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:557|altshift:oflow_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:558|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:558|addcore:adder|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:558|altshift:result_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:558|altshift:carry_ext_latency_ffs|
|fdiv_cnt:94|fdiv28_31:57|lpm_add_sub:558|altshift:oflow_ext_latency_ffs|