📄 fdiv28_31.rpt
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-- Node name is ':132'
-- Equation name is '_LC7_C6', type is buried
!_LC7_C6 = _LC7_C6~NOT;
_LC7_C6~NOT = LCELL( _EQ011);
_EQ011 = _LC6_C8
# _LC1_C8 & _LC8_C8
# _LC3_C9 & _LC8_C8;
-- Node name is '~232~1'
-- Equation name is '~232~1', location is LC3_C6, type is buried.
-- synthesized logic cell
_LC3_C6 = LCELL( _EQ012);
_EQ012 = _LC4_C2 & !_LC6_C8 & leapyear
# _LC7_C6 & !leapyear;
-- Node name is '~232~2'
-- Equation name is '~232~2', location is LC5_C9, type is buried.
-- synthesized logic cell
_LC5_C9 = LCELL( _EQ013);
_EQ013 = _LC3_C6 & !_LC3_C8;
-- Node name is '~281~1'
-- Equation name is '~281~1', location is LC3_A8, type is buried.
-- synthesized logic cell
!_LC3_A8 = _LC3_A8~NOT;
_LC3_A8~NOT = LCELL( _EQ014);
_EQ014 = !month0 & !month3 & !month4;
-- Node name is '~281~2'
-- Equation name is '~281~2', location is LC5_A8, type is buried.
-- synthesized logic cell
!_LC5_A8 = _LC5_A8~NOT;
_LC5_A8~NOT = LCELL( _EQ015);
_EQ015 = month0 & !month1 & month3 & !month4
# month0 & !month1 & !month3 & month4;
-- Node name is ':281'
-- Equation name is '_LC4_A8', type is buried
_LC4_A8 = LCELL( _EQ016);
_EQ016 = _LC1_A8 & !_LC3_A8 & month2
# _LC1_A8 & !_LC5_A8 & !month2;
-- Node name is ':292'
-- Equation name is '_LC1_C12', type is buried
!_LC1_C12 = _LC1_C12~NOT;
_LC1_C12~NOT = LCELL( _EQ017);
_EQ017 = _LC1_C8 & _LC8_C8;
-- Node name is ':396'
-- Equation name is '_LC6_C2', type is buried
!_LC6_C2 = _LC6_C2~NOT;
_LC6_C2~NOT = LCELL( _EQ018);
_EQ018 = _LC3_C9
# _LC2_C6
# _LC1_C9
# _LC7_C9;
-- Node name is '~481~1'
-- Equation name is '~481~1', location is LC6_C6, type is buried.
-- synthesized logic cell
_LC6_C6 = LCELL( _EQ019);
_EQ019 = !_LC4_A8 & _LC6_C2 & !_LC6_C8
# _LC1_C12 & !_LC6_C8;
-- Node name is '~481~2'
-- Equation name is '~481~2', location is LC4_C9, type is buried.
-- synthesized logic cell
_LC4_C9 = LCELL( _EQ020);
_EQ020 = !_LC3_C8 & _LC6_C6;
-- Node name is '~492~1'
-- Equation name is '~492~1', location is LC7_C8, type is buried.
-- synthesized logic cell
_LC7_C8 = LCELL( _EQ021);
_EQ021 = _LC1_C8 & _LC2_C6 & _LC3_C2
# _LC1_C8 & _LC5_C2;
-- Node name is '~494~1'
-- Equation name is '~494~1', location is LC4_C8, type is buried.
-- synthesized logic cell
_LC4_C8 = LCELL( _EQ022);
_EQ022 = !_LC2_A8 & _LC6_C6
# _LC2_A8 & _LC3_C6;
-- Node name is '~498~1'
-- Equation name is '~498~1', location is LC5_C6, type is buried.
-- synthesized logic cell
_LC5_C6 = LCELL( _EQ023);
_EQ023 = !_LC1_C12 & !_LC6_C2
# _LC6_C8
# !_LC1_C12 & _LC4_A8;
-- Node name is '~498~2'
-- Equation name is '~498~2', location is LC8_C6, type is buried.
-- synthesized logic cell
_LC8_C6 = LCELL( _EQ024);
_EQ024 = _LC6_C8 & leapyear
# !_LC4_C2 & leapyear
# !_LC7_C6 & !leapyear;
-- Node name is ':500'
-- Equation name is '_LC6_C8', type is buried
_LC6_C8 = DFFE( _EQ025, GLOBAL( clki), GLOBAL(!clr), VCC, VCC);
_EQ025 = _LC4_C8 & _LC7_C8 & _LC8_C8;
-- Node name is ':501'
-- Equation name is '_LC8_C8', type is buried
_LC8_C8 = DFFE( _EQ026, GLOBAL( clki), GLOBAL(!clr), VCC, VCC);
_EQ026 = _LC2_A8 & _LC3_C6 & _LC5_C8
# !_LC2_A8 & _LC5_C8 & _LC6_C6;
-- Node name is ':502'
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = DFFE( _EQ027, GLOBAL( clki), GLOBAL(!clr), VCC, VCC);
_EQ027 = !_LC1_C8 & _LC4_C8 & _LC5_C2
# !_LC1_C8 & _LC3_C8 & _LC4_C8
# _LC1_C8 & !_LC3_C8 & _LC4_C8 & !_LC5_C2;
-- Node name is ':503'
-- Equation name is '_LC3_C9', type is buried
_LC3_C9 = DFFE( _EQ028, GLOBAL( clki), GLOBAL(!clr), VCC, VCC);
_EQ028 = _LC2_A8 & _LC5_C9 & _LC8_C9
# !_LC2_A8 & _LC4_C9 & _LC8_C9;
-- Node name is ':504'
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = DFFE( _EQ029, GLOBAL( clki), GLOBAL(!clr), VCC, VCC);
_EQ029 = _LC2_A8 & _LC5_C9 & _LC6_C9
# !_LC2_A8 & _LC4_C9 & _LC6_C9;
-- Node name is ':505'
-- Equation name is '_LC7_C9', type is buried
_LC7_C9 = DFFE( _EQ030, GLOBAL( clki), GLOBAL(!clr), VCC, VCC);
_EQ030 = !_LC2_A8 & _LC2_C9 & _LC4_C9
# _LC2_A8 & _LC2_C9 & _LC5_C9;
-- Node name is ':506'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = DFFE( _EQ031, GLOBAL( clki), GLOBAL(!clr), VCC, VCC);
_EQ031 = !_LC2_A8 & _LC5_C6
# !_LC2_C6
# _LC2_A8 & _LC8_C6;
-- Node name is '~527~1'
-- Equation name is '~527~1', location is LC3_C2, type is buried.
-- synthesized logic cell
!_LC3_C2 = _LC3_C2~NOT;
_LC3_C2~NOT = LCELL( _EQ032);
_EQ032 = !_LC3_C9
# _LC1_C9
# _LC7_C9;
-- Node name is '~528~1'
-- Equation name is '~528~1', location is LC1_C6, type is buried.
-- synthesized logic cell
_LC1_C6 = LCELL( _EQ033);
_EQ033 = _LC2_C6 & !_LC6_C8 & _LC8_C8 & leapyear
# !_LC2_C6 & !_LC6_C8 & _LC8_C8 & !leapyear;
-- Node name is ':528'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = LCELL( _EQ034);
_EQ034 = _LC1_C6 & !_LC1_C8 & _LC2_A8 & _LC3_C2;
-- Node name is '~550~1'
-- Equation name is '~550~1', location is LC4_C6, type is buried.
-- synthesized logic cell
_LC4_C6 = LCELL( _EQ035);
_EQ035 = !_LC2_C6 & !_LC3_C9 & _LC4_A8 & !_LC6_C8
# _LC2_C6 & !_LC3_C9 & !_LC4_A8 & !_LC6_C8;
-- Node name is '~550~2'
-- Equation name is '~550~2', location is LC8_C2, type is buried.
-- synthesized logic cell
_LC8_C2 = LCELL( _EQ036);
_EQ036 = !_LC1_C9 & !_LC2_A8 & _LC4_C6 & !_LC7_C9;
-- Node name is ':552'
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = DFFE( _EQ037, GLOBAL( clki), VCC, VCC, !_LC2_C2);
_EQ037 = !_LC1_C12 & _LC8_C2
# _LC2_C8;
Project Information e:\amj\eda\experiment\calendar_clock\fdiv28_31.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,817K
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