📄 fdiv28_31.rpt
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Device-Specific Information:e:\amj\eda\experiment\calendar_clock\fdiv28_31.rpt
fdiv28_31
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
30 - - C -- OUTPUT 0 1 0 0 clko
28 - - C -- OUTPUT 0 1 0 0 cnt0
58 - - C -- OUTPUT 0 1 0 0 cnt1
27 - - C -- OUTPUT 0 1 0 0 cnt2
61 - - C -- OUTPUT 0 1 0 0 cnt3
62 - - C -- OUTPUT 0 1 0 0 cnt4
29 - - C -- OUTPUT 0 1 0 0 cnt5
36 - - - 07 OUTPUT 0 1 0 0 cnt6
23 - - B -- OUTPUT 0 0 0 0 cnt7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\fdiv28_31.rpt
fdiv28_31
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 02 SOFT s ! 1 0 0 1 clr~1
- 5 - C 02 OR2 ! 0 4 0 3 |lpm_add_sub:555|addcore:adder|:129
- 2 - C 09 OR2 0 2 0 1 |lpm_add_sub:555|addcore:adder|:149
- 6 - C 09 OR2 0 3 0 1 |lpm_add_sub:555|addcore:adder|:150
- 8 - C 09 OR2 0 4 0 1 |lpm_add_sub:555|addcore:adder|:151
- 1 - A 08 AND2 s 3 0 0 2 ~21~1
- 2 - A 08 AND2 2 2 0 8 :21
- 4 - C 02 OR2 ! 0 4 0 2 :43
- 1 - C 02 OR2 ! 0 3 0 1 :55
- 3 - C 08 OR2 ! 0 2 0 4 :74
- 5 - C 08 OR2 0 4 0 1 :99
- 7 - C 06 OR2 ! 0 4 0 2 :132
- 3 - C 06 OR2 s 1 3 0 3 ~232~1
- 5 - C 09 AND2 s 0 2 0 3 ~232~2
- 3 - A 08 AND2 s ! 3 0 0 2 ~281~1
- 5 - A 08 OR2 s ! 4 0 0 1 ~281~2
- 4 - A 08 OR2 1 3 0 3 :281
- 1 - C 12 AND2 ! 0 2 0 3 :292
- 6 - C 02 OR2 ! 0 4 0 2 :396
- 6 - C 06 OR2 s 0 4 0 3 ~481~1
- 4 - C 09 AND2 s 0 2 0 3 ~481~2
- 7 - C 08 OR2 s 0 4 0 1 ~492~1
- 4 - C 08 OR2 s 0 3 0 2 ~494~1
- 5 - C 06 OR2 s 0 4 0 1 ~498~1
- 8 - C 06 OR2 s 1 3 0 1 ~498~2
- 6 - C 08 DFFE + 0 3 1 7 :500
- 8 - C 08 DFFE + 0 4 1 6 :501
- 1 - C 08 DFFE + 0 3 1 6 :502
- 3 - C 09 DFFE + 0 4 1 7 :503
- 1 - C 09 DFFE + 0 4 1 7 :504
- 7 - C 09 DFFE + 0 4 1 8 :505
- 2 - C 06 DFFE + 0 3 1 10 :506
- 3 - C 02 OR2 s ! 0 3 0 3 ~527~1
- 1 - C 06 OR2 s 1 3 0 1 ~528~1
- 2 - C 08 AND2 0 4 0 1 :528
- 4 - C 06 OR2 s 0 4 0 1 ~550~1
- 8 - C 02 AND2 s 0 4 0 1 ~550~2
- 7 - C 02 DFFE + 0 4 1 0 :552
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\fdiv28_31.rpt
fdiv28_31
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 0/ 48( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 5/ 96( 5%) 22/ 48( 45%) 0/ 48( 0%) 1/16( 6%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\fdiv28_31.rpt
fdiv28_31
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clki
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\fdiv28_31.rpt
fdiv28_31
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 clr
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\fdiv28_31.rpt
fdiv28_31
** EQUATIONS **
clki : INPUT;
clr : INPUT;
leapyear : INPUT;
month0 : INPUT;
month1 : INPUT;
month2 : INPUT;
month3 : INPUT;
month4 : INPUT;
month5 : INPUT;
month6 : INPUT;
month7 : INPUT;
-- Node name is 'clko'
-- Equation name is 'clko', type is output
clko = _LC7_C2;
-- Node name is 'clr~1'
-- Equation name is 'clr~1', location is LC2_C2, type is buried.
-- synthesized logic cell
!_LC2_C2 = _LC2_C2~NOT;
_LC2_C2~NOT = LCELL(!clr);
-- Node name is 'cnt0'
-- Equation name is 'cnt0', type is output
cnt0 = _LC2_C6;
-- Node name is 'cnt1'
-- Equation name is 'cnt1', type is output
cnt1 = _LC7_C9;
-- Node name is 'cnt2'
-- Equation name is 'cnt2', type is output
cnt2 = _LC1_C9;
-- Node name is 'cnt3'
-- Equation name is 'cnt3', type is output
cnt3 = _LC3_C9;
-- Node name is 'cnt4'
-- Equation name is 'cnt4', type is output
cnt4 = _LC1_C8;
-- Node name is 'cnt5'
-- Equation name is 'cnt5', type is output
cnt5 = _LC8_C8;
-- Node name is 'cnt6'
-- Equation name is 'cnt6', type is output
cnt6 = _LC6_C8;
-- Node name is 'cnt7'
-- Equation name is 'cnt7', type is output
cnt7 = GND;
-- Node name is '|lpm_add_sub:555|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C2', type is buried
!_LC5_C2 = _LC5_C2~NOT;
_LC5_C2~NOT = LCELL( _EQ001);
_EQ001 = !_LC7_C9
# !_LC2_C6
# !_LC1_C9
# !_LC3_C9;
-- Node name is '|lpm_add_sub:555|addcore:adder|:149' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_C9', type is buried
_LC2_C9 = LCELL( _EQ002);
_EQ002 = !_LC2_C6 & _LC7_C9
# _LC2_C6 & !_LC7_C9;
-- Node name is '|lpm_add_sub:555|addcore:adder|:150' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_C9', type is buried
_LC6_C9 = LCELL( _EQ003);
_EQ003 = _LC1_C9 & !_LC7_C9
# _LC1_C9 & !_LC2_C6
# !_LC1_C9 & _LC2_C6 & _LC7_C9;
-- Node name is '|lpm_add_sub:555|addcore:adder|:151' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_C9', type is buried
_LC8_C9 = LCELL( _EQ004);
_EQ004 = _LC3_C9 & !_LC7_C9
# !_LC2_C6 & _LC3_C9
# !_LC1_C9 & _LC3_C9
# _LC1_C9 & _LC2_C6 & !_LC3_C9 & _LC7_C9;
-- Node name is '~21~1'
-- Equation name is '~21~1', location is LC1_A8, type is buried.
-- synthesized logic cell
_LC1_A8 = LCELL( _EQ005);
_EQ005 = !month5 & !month6 & !month7;
-- Node name is ':21'
-- Equation name is '_LC2_A8', type is buried
_LC2_A8 = LCELL( _EQ006);
_EQ006 = _LC1_A8 & !_LC3_A8 & month1 & !month2;
-- Node name is ':43'
-- Equation name is '_LC4_C2', type is buried
!_LC4_C2 = _LC4_C2~NOT;
_LC4_C2~NOT = LCELL( _EQ007);
_EQ007 = _LC1_C8 & _LC8_C8
# !_LC1_C2 & _LC3_C9 & _LC8_C8;
-- Node name is ':55'
-- Equation name is '_LC1_C2', type is buried
!_LC1_C2 = _LC1_C2~NOT;
_LC1_C2~NOT = LCELL( _EQ008);
_EQ008 = _LC2_C6
# _LC1_C9
# _LC7_C9;
-- Node name is ':74'
-- Equation name is '_LC3_C8', type is buried
!_LC3_C8 = _LC3_C8~NOT;
_LC3_C8~NOT = LCELL( _EQ009);
_EQ009 = !_LC3_C2
# !_LC2_C6;
-- Node name is ':99'
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = LCELL( _EQ010);
_EQ010 = _LC1_C8 & _LC3_C8 & !_LC8_C8
# !_LC1_C8 & _LC8_C8
# !_LC3_C8 & !_LC5_C2 & _LC8_C8
# _LC1_C8 & _LC5_C2 & !_LC8_C8;
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