📄 fdiv_cnt.rpt
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- 4 - A 02 OR2 0 3 0 1 |fdiv28_31:57|lpm_add_sub:555|addcore:adder|:150
- 5 - A 02 OR2 0 4 0 1 |fdiv28_31:57|lpm_add_sub:555|addcore:adder|:151
- 4 - C 02 AND2 s 0 4 0 2 |fdiv28_31:57|~21~1
- 6 - C 02 OR2 ! 0 2 0 7 |fdiv28_31:57|:21
- 5 - A 12 OR2 ! 0 4 0 2 |fdiv28_31:57|:43
- 3 - A 03 OR2 ! 0 3 0 1 |fdiv28_31:57|:55
- 7 - A 03 OR2 ! 0 2 0 4 |fdiv28_31:57|:74
- 6 - A 04 OR2 0 4 0 1 |fdiv28_31:57|:99
- 6 - A 12 OR2 ! 0 4 0 2 |fdiv28_31:57|:132
- 4 - A 12 OR2 s 0 4 0 3 |fdiv28_31:57|~232~1
- 1 - A 04 AND2 s 0 2 0 3 |fdiv28_31:57|~232~2
- 8 - C 02 OR2 s 0 4 0 1 |fdiv28_31:57|~281~1
- 1 - C 02 OR2 ! 0 4 0 3 |fdiv28_31:57|:281
- 1 - A 12 AND2 ! 0 2 0 3 |fdiv28_31:57|:292
- 7 - A 02 OR2 ! 0 4 0 2 |fdiv28_31:57|:396
- 3 - A 12 OR2 s 0 4 0 3 |fdiv28_31:57|~481~1
- 7 - A 04 AND2 s 0 2 0 3 |fdiv28_31:57|~481~2
- 8 - A 04 OR2 s 0 4 0 1 |fdiv28_31:57|~492~1
- 5 - A 04 OR2 s 0 3 0 2 |fdiv28_31:57|~494~1
- 2 - A 12 OR2 s 0 4 0 1 |fdiv28_31:57|~498~1
- 7 - A 12 OR2 s 0 4 0 1 |fdiv28_31:57|~498~2
- 4 - A 04 DFFE 0 4 1 7 |fdiv28_31:57|:500
- 3 - A 04 DFFE 0 5 1 6 |fdiv28_31:57|:501
- 2 - A 04 DFFE 0 4 1 6 |fdiv28_31:57|:502
- 6 - A 02 DFFE 0 5 1 7 |fdiv28_31:57|:503
- 8 - A 02 DFFE 0 5 1 7 |fdiv28_31:57|:504
- 3 - A 02 DFFE 0 5 1 8 |fdiv28_31:57|:505
- 8 - A 12 DFFE 0 4 1 10 |fdiv28_31:57|:506
- 2 - A 03 AND2 s 0 3 0 1 |fdiv28_31:57|~527~1
- 1 - A 03 AND2 s 0 3 0 3 |fdiv28_31:57|~527~2
- 5 - A 03 OR2 0 4 0 1 |fdiv28_31:57|:527
- 6 - A 03 AND2 s 0 4 0 1 |fdiv28_31:57|~549~1
- 8 - A 03 OR2 0 4 0 1 |fdiv28_31:57|:549
- 4 - A 03 DFFE 0 5 1 1 |fdiv28_31:57|:552
- 7 - B 02 AND2 s 0 3 0 1 |fdiv60:53|lpm_add_sub:96|addcore:adder|~137~1
- 7 - B 01 OR2 0 4 0 2 |fdiv60:53|lpm_add_sub:96|addcore:adder|:137
- 2 - B 01 AND2 0 3 0 3 |fdiv60:53|lpm_add_sub:97|addcore:adder|:125
- 5 - B 02 AND2 0 2 0 2 |fdiv60:53|lpm_add_sub:97|addcore:adder|:129
- 3 - B 02 AND2 0 4 0 2 |fdiv60:53|lpm_add_sub:97|addcore:adder|:137
- 1 - B 01 OR2 ! 0 4 0 9 |fdiv60:53|:30
- 7 - B 10 OR2 0 4 0 1 |fdiv60:53|:36
- 8 - B 10 OR2 0 4 0 1 |fdiv60:53|:45
- 5 - B 10 OR2 0 4 0 1 |fdiv60:53|:54
- 8 - B 02 OR2 0 4 0 1 |fdiv60:53|:55
- 3 - B 10 DFFE 0 5 1 3 |fdiv60:53|:77
- 4 - B 10 DFFE 0 4 1 4 |fdiv60:53|:78
- 1 - B 02 DFFE 0 4 1 4 |fdiv60:53|:79
- 2 - B 02 DFFE 0 4 1 7 |fdiv60:53|:80
- 6 - B 02 DFFE 0 3 1 4 |fdiv60:53|:81
- 5 - B 01 DFFE 0 4 1 3 |fdiv60:53|:82
- 3 - B 01 DFFE 0 3 1 4 |fdiv60:53|:83
- 8 - B 01 DFFE 0 1 1 5 |fdiv60:53|:84
- 1 - B 10 OR2 s ! 0 4 0 5 |fdiv60:53|~85~1
- 4 - B 02 DFFE 0 3 1 1 |fdiv60:53|:95
- 2 - A 22 AND2 s 0 3 0 1 |fdiv60:54|lpm_add_sub:96|addcore:adder|~137~1
- 1 - A 21 OR2 0 4 0 2 |fdiv60:54|lpm_add_sub:96|addcore:adder|:137
- 8 - A 21 AND2 0 3 0 3 |fdiv60:54|lpm_add_sub:97|addcore:adder|:125
- 6 - A 22 AND2 0 2 0 2 |fdiv60:54|lpm_add_sub:97|addcore:adder|:129
- 5 - A 22 AND2 0 4 0 2 |fdiv60:54|lpm_add_sub:97|addcore:adder|:137
- 2 - A 19 OR2 s 0 4 0 5 |fdiv60:54|~12~1
- 4 - A 21 OR2 ! 0 4 0 9 |fdiv60:54|:30
- 7 - A 19 OR2 0 4 0 1 |fdiv60:54|:36
- 8 - A 19 OR2 0 4 0 1 |fdiv60:54|:45
- 5 - A 19 OR2 0 4 0 1 |fdiv60:54|:54
- 7 - A 22 OR2 0 4 0 1 |fdiv60:54|:55
- 1 - A 19 DFFE 0 5 1 3 |fdiv60:54|:77
- 6 - A 19 DFFE 0 4 1 4 |fdiv60:54|:78
- 1 - A 22 DFFE 0 4 1 4 |fdiv60:54|:79
- 3 - A 22 DFFE 0 4 1 7 |fdiv60:54|:80
- 4 - A 22 DFFE 0 3 1 4 |fdiv60:54|:81
- 6 - A 21 DFFE 0 4 1 3 |fdiv60:54|:82
- 5 - A 21 DFFE 0 3 1 4 |fdiv60:54|:83
- 7 - A 21 DFFE 0 1 1 5 |fdiv60:54|:84
- 4 - A 19 DFFE 0 3 1 1 |fdiv60:54|:95
- 6 - B 10 LCELL s 1 0 1 0 s_clk~1
- 2 - B 10 OR2 2 0 0 9 :63
- 3 - A 21 OR2 1 1 0 9 :64
- 3 - A 19 OR2 1 1 0 9 :65
- 2 - A 15 OR2 1 1 0 4 :66
- 3 - A 07 OR2 1 1 0 8 :67
- 1 - C 11 OR2 1 1 0 6 :68
- 3 - C 21 OR2 1 1 0 9 :69
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\fdiv_cnt.rpt
fdiv_cnt
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/ 96( 10%) 18/ 48( 37%) 16/ 48( 33%) 0/16( 0%) 16/16(100%) 0/16( 0%)
B: 0/ 96( 0%) 14/ 48( 29%) 13/ 48( 27%) 0/16( 0%) 14/16( 87%) 0/16( 0%)
C: 5/ 96( 5%) 9/ 48( 18%) 25/ 48( 52%) 1/16( 6%) 13/16( 81%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\fdiv_cnt.rpt
fdiv_cnt
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 9 :63
LCELL 9 :64
LCELL 9 :65
LCELL 9 :69
LCELL 8 :67
LCELL 6 :68
LCELL 4 :66
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\fdiv_cnt.rpt
fdiv_cnt
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 25 clr_date
INPUT 24 clr_time
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\fdiv_cnt.rpt
fdiv_cnt
** EQUATIONS **
clk : INPUT;
clr_date : INPUT;
clr_time : INPUT;
set_day : INPUT;
set_hr : INPUT;
set_min : INPUT;
set_mon : INPUT;
set_sec : INPUT;
set_week : INPUT;
set_year : INPUT;
-- Node name is 'clr_date~1'
-- Equation name is 'clr_date~1', location is LC1_C23, type is buried.
-- synthesized logic cell
!_LC1_C23 = _LC1_C23~NOT;
_LC1_C23~NOT = LCELL(!clr_date);
-- Node name is 'day_clk'
-- Equation name is 'day_clk', type is output
day_clk = _LC4_B14;
-- Node name is 'day0'
-- Equation name is 'day0', type is output
day0 = _LC8_A12;
-- Node name is 'day1'
-- Equation name is 'day1', type is output
day1 = _LC3_A2;
-- Node name is 'day2'
-- Equation name is 'day2', type is output
day2 = _LC8_A2;
-- Node name is 'day3'
-- Equation name is 'day3', type is output
day3 = _LC6_A2;
-- Node name is 'day4'
-- Equation name is 'day4', type is output
day4 = _LC2_A4;
-- Node name is 'day5'
-- Equation name is 'day5', type is output
day5 = _LC3_A4;
-- Node name is 'day6'
-- Equation name is 'day6', type is output
day6 = _LC4_A4;
-- Node name is 'day7'
-- Equation name is 'day7', type is output
day7 = GND;
-- Node name is 'h_clk'
-- Equation name is 'h_clk', type is output
h_clk = _LC4_A19;
-- Node name is 'hr0'
-- Equation name is 'hr0', type is output
hr0 = _LC6_B14;
-- Node name is 'hr1'
-- Equation name is 'hr1', type is output
hr1 = _LC8_B14;
-- Node name is 'hr2'
-- Equation name is 'hr2', type is output
hr2 = _LC6_B15;
-- Node name is 'hr3'
-- Equation name is 'hr3', type is output
hr3 = _LC1_B15;
-- Node name is 'hr4'
-- Equation name is 'hr4', type is output
hr4 = _LC4_B15;
-- Node name is 'hr5'
-- Equation name is 'hr5', type is output
hr5 = _LC3_B15;
-- Node name is 'hr6'
-- Equation name is 'hr6', type is output
hr6 = _LC7_B23;
-- Node name is 'hr7'
-- Equation name is 'hr7', type is output
hr7 = _LC2_B23;
-- Node name is 'min_clk'
-- Equation name is 'min_clk', type is output
min_clk = _LC4_B2;
-- Node name is 'min0'
-- Equation name is 'min0', type is output
min0 = _LC7_A21;
-- Node name is 'min1'
-- Equation name is 'min1', type is output
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