📄 fdiv_cnt.rpt
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A2 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 5/22( 22%)
A3 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 13/22( 59%)
A4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
A7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
A15 5/ 8( 62%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 2/22( 9%)
A19 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 7/22( 31%)
A21 7/ 8( 87%) 1/ 8( 12%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
A22 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 4/22( 18%)
B1 6/ 8( 75%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
B2 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 4/22( 18%)
B10 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
B14 7/ 8( 87%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 7/22( 31%)
B15 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 4/22( 18%)
B23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 10/22( 45%)
C2 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
C9 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
C11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C14 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 1/2 4/22( 18%)
C15 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 16/22( 72%)
C18 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
C19 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
C21 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 7/22( 31%)
C23 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 62/96 ( 64%)
Total logic cells used: 162/576 ( 28%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.25/4 ( 81%)
Total fan-in: 527/2304 ( 22%)
Total input pins required: 10
Total input I/O cell registers required: 0
Total output pins required: 58
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 162
Total flipflops required: 54
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 32/ 576 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 8 8 8 0 0 1 0 0 0 0 8 0 0 0 5 0 0 0 8 0 7 7 0 0 60/0
B: 6 8 0 0 0 0 0 0 0 8 0 0 0 0 7 8 0 0 0 0 0 0 0 8 0 45/0
C: 0 8 0 0 0 0 0 0 8 0 1 0 0 0 8 8 0 0 8 8 0 7 0 1 0 57/0
Total: 6 24 8 8 0 0 1 0 8 8 1 8 0 0 15 21 0 0 8 16 0 14 7 9 0 162/0
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\fdiv_cnt.rpt
fdiv_cnt
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT 0 0 0 2 clk
56 - - - -- INPUT G 0 0 0 1 clr_date
54 - - - -- INPUT G 0 0 0 0 clr_time
62 - - - 11 INPUT 0 0 0 1 set_day
124 - - - -- INPUT 0 0 0 1 set_hr
125 - - - -- INPUT 0 0 0 1 set_min
81 - - C -- INPUT 0 0 0 1 set_mon
126 - - - -- INPUT 0 0 0 1 set_sec
144 - - - 24 INPUT 0 0 0 1 set_week
51 - - - 13 INPUT 0 0 0 1 set_year
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\fdiv_cnt.rpt
fdiv_cnt
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
128 - - - 13 OUTPUT 0 1 0 0 day_clk
98 - - A -- OUTPUT 0 1 0 0 day0
99 - - A -- OUTPUT 0 1 0 0 day1
95 - - A -- OUTPUT 0 1 0 0 day2
96 - - A -- OUTPUT 0 1 0 0 day3
101 - - A -- OUTPUT 0 1 0 0 day4
100 - - A -- OUTPUT 0 1 0 0 day5
102 - - A -- OUTPUT 0 1 0 0 day6
68 - - - 07 OUTPUT 0 0 0 0 day7
137 - - - 19 OUTPUT 0 1 0 0 h_clk
22 - - B -- OUTPUT 0 1 0 0 hr0
21 - - B -- OUTPUT 0 1 0 0 hr1
48 - - - 15 OUTPUT 0 1 0 0 hr2
17 - - B -- OUTPUT 0 1 0 0 hr3
20 - - B -- OUTPUT 0 1 0 0 hr4
19 - - B -- OUTPUT 0 1 0 0 hr5
23 - - B -- OUTPUT 0 1 0 0 hr6
18 - - B -- OUTPUT 0 1 0 0 hr7
111 - - - 02 OUTPUT 0 1 0 0 min_clk
13 - - A -- OUTPUT 0 1 0 0 min0
39 - - - 21 OUTPUT 0 1 0 0 min1
12 - - A -- OUTPUT 0 1 0 0 min2
10 - - A -- OUTPUT 0 1 0 0 min3
9 - - A -- OUTPUT 0 1 0 0 min4
8 - - A -- OUTPUT 0 1 0 0 min5
97 - - A -- OUTPUT 0 1 0 0 min6
7 - - A -- OUTPUT 0 1 0 0 min7
113 - - - 03 OUTPUT 0 1 0 0 mon_clk
79 - - C -- OUTPUT 0 1 0 0 mon0
83 - - C -- OUTPUT 0 1 0 0 mon1
78 - - C -- OUTPUT 0 1 0 0 mon2
82 - - C -- OUTPUT 0 1 0 0 mon3
80 - - C -- OUTPUT 0 1 0 0 mon4
73 - - - 02 OUTPUT 0 0 0 0 mon5
44 - - - 18 OUTPUT 0 0 0 0 mon6
60 - - - 12 OUTPUT 0 0 0 0 mon7
87 - - B -- OUTPUT 0 1 0 0 s_clk
86 - - B -- OUTPUT 0 1 0 0 sec0
110 - - - 01 OUTPUT 0 1 0 0 sec1
89 - - B -- OUTPUT 0 1 0 0 sec2
88 - - B -- OUTPUT 0 1 0 0 sec3
91 - - B -- OUTPUT 0 1 0 0 sec4
92 - - B -- OUTPUT 0 1 0 0 sec5
90 - - B -- OUTPUT 0 1 0 0 sec6
64 - - - 10 OUTPUT 0 1 0 0 sec7
11 - - A -- OUTPUT 0 1 0 0 week0
14 - - A -- OUTPUT 0 1 0 0 week1
47 - - - 16 OUTPUT 0 1 0 0 week2
131 - - - 15 OUTPUT 0 1 0 0 week3
30 - - C -- OUTPUT 0 1 0 0 year_clk
31 - - C -- OUTPUT 0 1 0 0 year0
32 - - C -- OUTPUT 0 1 0 0 year1
28 - - C -- OUTPUT 0 1 0 0 year2
49 - - - 14 OUTPUT 0 1 0 0 year3
29 - - C -- OUTPUT 0 1 0 0 year4
26 - - C -- OUTPUT 0 1 0 0 year5
27 - - C -- OUTPUT 0 1 0 0 year6
33 - - C -- OUTPUT 0 1 0 0 year7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\fdiv_cnt.rpt
fdiv_cnt
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 23 SOFT s ! 1 0 0 2 clr_date~1
- 8 - C 18 AND2 0 4 0 1 |fdivyear:59|lpm_add_sub:370|addcore:adder|:141
- 5 - C 18 OR2 0 4 0 1 |fdivyear:59|lpm_add_sub:370|addcore:adder|:154
- 6 - C 14 AND2 0 3 0 1 |fdivyear:59|lpm_add_sub:371|addcore:adder|:125
- 1 - C 14 AND2 0 4 0 6 |fdivyear:59|lpm_add_sub:371|addcore:adder|:129
- 7 - C 18 AND2 0 4 0 2 |fdivyear:59|lpm_add_sub:371|addcore:adder|:141
- 3 - C 18 OR2 0 3 0 1 |fdivyear:59|lpm_add_sub:371|addcore:adder|:153
- 6 - C 18 OR2 0 4 0 2 |fdivyear:59|lpm_add_sub:371|addcore:adder|:154
- 5 - C 21 OR2 0 4 0 12 |fdivyear:59|:12
- 6 - C 21 OR2 0 2 0 1 |fdivyear:59|:27
- 8 - C 14 OR2 0 4 0 9 |fdivyear:59|:62
- 3 - C 19 OR2 ! 0 3 0 1 |fdivyear:59|:64
- 7 - C 14 OR2 0 3 0 3 |fdivyear:59|:93
- 4 - C 18 OR2 0 4 0 3 |fdivyear:59|:97
- 1 - C 18 OR2 0 3 0 2 |fdivyear:59|:98
- 2 - C 18 OR2 0 4 0 2 |fdivyear:59|:99
- 8 - C 19 OR2 0 4 0 2 |fdivyear:59|:100
- 4 - C 14 OR2 0 4 0 2 |fdivyear:59|:102
- 2 - C 19 OR2 0 3 0 3 |fdivyear:59|:103
- 6 - C 15 AND2 0 2 0 4 |fdivyear:59|:106
- 4 - C 21 AND2 0 2 0 4 |fdivyear:59|:107
- 8 - C 21 DFFE 0 3 1 3 |fdivyear:59|:121
- 2 - C 21 DFFE 0 2 1 5 |fdivyear:59|:122
- 1 - C 21 DFFE 0 2 1 7 |fdivyear:59|:123
- 4 - C 19 DFFE 0 3 1 9 |fdivyear:59|:124
- 5 - C 14 DFFE 0 3 1 4 |fdivyear:59|:125
- 2 - C 14 DFFE 0 3 1 6 |fdivyear:59|:126
- 7 - C 19 DFFE 0 3 1 7 |fdivyear:59|:127
- 6 - C 19 DFFE 0 2 1 7 |fdivyear:59|:128
- 3 - C 14 AND2 s 0 4 0 1 |fdivyear:59|~367~1
- 1 - C 15 OR2 s 0 4 0 1 |fdivyear:59|~367~2
- 2 - C 15 AND2 s 0 4 0 2 |fdivyear:59|~367~3
- 4 - C 15 OR2 s 0 4 0 1 |fdivyear:59|~367~4
- 5 - C 15 OR2 s 0 4 0 1 |fdivyear:59|~367~5
- 1 - C 19 OR2 s 0 4 0 1 |fdivyear:59|~367~6
- 5 - C 19 OR2 s 0 4 0 1 |fdivyear:59|~367~7
- 7 - C 15 OR2 s 0 4 0 1 |fdivyear:59|~367~8
- 8 - C 15 OR2 s 0 4 0 1 |fdivyear:59|~367~9
- 3 - C 15 DFFE 0 5 0 3 |fdivyear:59|:368
- 1 - A 15 DFFE 0 4 1 1 |fdiv7:58|:24
- 6 - A 15 DFFE 0 3 1 2 |fdiv7:58|:25
- 8 - A 15 DFFE 0 2 1 3 |fdiv7:58|:26
- 5 - A 15 DFFE ! 0 4 1 3 |fdiv7:58|:27
- 6 - C 09 AND2 0 3 0 1 |fdiv12:70|lpm_add_sub:119|addcore:adder|:125
- 8 - C 09 AND2 0 4 0 1 |fdiv12:70|lpm_add_sub:119|addcore:adder|:129
- 2 - C 02 OR2 0 4 0 5 |fdiv12:70|:27
- 7 - C 02 OR2 s ! 0 3 0 1 |fdiv12:70|~53~1
- 3 - C 02 OR2 ! 0 4 0 5 |fdiv12:70|:53
- 3 - C 09 AND2 s 0 2 0 1 |fdiv12:70|~88~1
- 4 - C 09 DFFE 0 4 1 5 |fdiv12:70|:103
- 2 - C 09 DFFE 0 4 1 5 |fdiv12:70|:104
- 7 - C 09 DFFE 0 4 1 7 |fdiv12:70|:105
- 1 - C 09 DFFE 0 4 1 7 |fdiv12:70|:106
- 5 - C 09 DFFE ! 0 2 1 8 |fdiv12:70|:107
- 5 - C 02 DFFE 0 3 1 1 |fdiv12:70|:118
- 1 - B 23 AND2 s 0 3 0 1 |fdiv24:55|lpm_add_sub:96|addcore:adder|~137~1
- 3 - B 23 OR2 0 4 0 2 |fdiv24:55|lpm_add_sub:96|addcore:adder|:137
- 6 - B 23 OR2 0 3 0 1 |fdiv24:55|lpm_add_sub:96|addcore:adder|:155
- 1 - B 14 OR2 ! 0 2 0 6 |fdiv24:55|lpm_add_sub:97|addcore:adder|:121
- 5 - B 15 AND2 0 2 0 1 |fdiv24:55|lpm_add_sub:97|addcore:adder|:125
- 7 - B 15 AND2 0 3 0 1 |fdiv24:55|lpm_add_sub:97|addcore:adder|:129
- 2 - B 15 AND2 0 4 0 3 |fdiv24:55|lpm_add_sub:97|addcore:adder|:133
- 4 - B 23 AND2 0 2 0 1 |fdiv24:55|lpm_add_sub:97|addcore:adder|:137
- 8 - B 23 OR2 0 4 0 1 |fdiv24:55|lpm_add_sub:97|addcore:adder|:155
- 5 - B 14 OR2 s 0 4 0 2 |fdiv24:55|~12~1
- 2 - B 14 OR2 ! 0 4 0 7 |fdiv24:55|:12
- 3 - B 14 OR2 ! 0 4 0 7 |fdiv24:55|:30
- 5 - B 23 OR2 0 4 0 1 |fdiv24:55|:54
- 8 - B 15 OR2 0 4 0 1 |fdiv24:55|:55
- 2 - B 23 DFFE 0 5 1 3 |fdiv24:55|:77
- 7 - B 23 DFFE 0 3 1 5 |fdiv24:55|:78
- 3 - B 15 DFFE 0 3 1 5 |fdiv24:55|:79
- 4 - B 15 DFFE 0 4 1 5 |fdiv24:55|:80
- 1 - B 15 DFFE 0 4 1 5 |fdiv24:55|:81
- 6 - B 15 DFFE 0 4 1 6 |fdiv24:55|:82
- 8 - B 14 DFFE 0 4 1 3 |fdiv24:55|:83
- 6 - B 14 DFFE 0 1 1 4 |fdiv24:55|:84
- 4 - B 14 DFFE 0 5 1 2 |fdiv24:55|:95
- 1 - A 02 OR2 ! 0 4 0 3 |fdiv28_31:57|lpm_add_sub:555|addcore:adder|:129
- 2 - A 02 OR2 0 2 0 1 |fdiv28_31:57|lpm_add_sub:555|addcore:adder|:149
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