📄 fdiv7.rpt
字号:
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 16 OR2 ! 0 4 0 4 :8
- 5 - A 16 DFFE + 0 3 1 1 :24
- 1 - A 16 DFFE + 0 3 1 2 :25
- 3 - A 16 DFFE + 0 2 1 3 :26
- 8 - A 16 DFFE + ! 0 1 1 4 :27
- 2 - A 16 DFFE + 0 1 1 0 :29
- 6 - A 16 AND2 ! 1 1 0 1 :31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\eda\2005\experiment\calendar_clock\fdiv7.rpt
fdiv7
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\2005\experiment\calendar_clock\fdiv7.rpt
fdiv7
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clki
Device-Specific Information:e:\amj\eda\2005\experiment\calendar_clock\fdiv7.rpt
fdiv7
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 clr
Device-Specific Information:e:\amj\eda\2005\experiment\calendar_clock\fdiv7.rpt
fdiv7
** EQUATIONS **
clki : INPUT;
clr : INPUT;
-- Node name is 'clko'
-- Equation name is 'clko', type is output
clko = _LC2_A16;
-- Node name is 'cnt0'
-- Equation name is 'cnt0', type is output
cnt0 = _LC8_A16;
-- Node name is 'cnt1'
-- Equation name is 'cnt1', type is output
cnt1 = _LC3_A16;
-- Node name is 'cnt2'
-- Equation name is 'cnt2', type is output
cnt2 = _LC1_A16;
-- Node name is 'cnt3'
-- Equation name is 'cnt3', type is output
cnt3 = _LC5_A16;
-- Node name is ':8'
-- Equation name is '_LC4_A16', type is buried
!_LC4_A16 = _LC4_A16~NOT;
_LC4_A16~NOT = LCELL( _EQ001);
_EQ001 = _LC5_A16
# !_LC1_A16
# !_LC3_A16
# !_LC8_A16;
-- Node name is ':24'
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = DFFE( _EQ002, GLOBAL( clki), GLOBAL(!clr), VCC, VCC);
_EQ002 = !_LC3_A16 & _LC5_A16
# _LC5_A16 & !_LC8_A16
# !_LC1_A16 & _LC5_A16;
-- Node name is ':25'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = DFFE( _EQ003, GLOBAL( clki), GLOBAL(!clr), VCC, VCC);
_EQ003 = _LC1_A16 & !_LC3_A16 & !_LC4_A16
# _LC1_A16 & !_LC4_A16 & !_LC8_A16
# !_LC1_A16 & _LC3_A16 & !_LC4_A16 & _LC8_A16;
-- Node name is ':26'
-- Equation name is '_LC3_A16', type is buried
_LC3_A16 = DFFE( _EQ004, GLOBAL( clki), GLOBAL(!clr), VCC, VCC);
_EQ004 = _LC3_A16 & !_LC4_A16 & !_LC8_A16
# !_LC3_A16 & !_LC4_A16 & _LC8_A16;
-- Node name is ':27'
-- Equation name is '_LC8_A16', type is buried
!_LC8_A16 = _LC8_A16~NOT;
_LC8_A16~NOT = DFFE( _EQ005, GLOBAL( clki), GLOBAL(!clr), VCC, VCC);
_EQ005 = !_LC4_A16 & _LC8_A16;
-- Node name is ':29'
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = DFFE( VCC, GLOBAL( clki), VCC, VCC, !_LC6_A16);
-- Node name is ':31'
-- Equation name is '_LC6_A16', type is buried
!_LC6_A16 = _LC6_A16~NOT;
_LC6_A16~NOT = LCELL( _EQ006);
_EQ006 = !clr & _LC4_A16;
Project Information e:\amj\eda\2005\experiment\calendar_clock\fdiv7.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,191K
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