📄 route.rpt
字号:
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 7/ 48( 14%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\route.rpt
route
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk_4Hz
INPUT 4 mode
INPUT 2 select
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\route.rpt
route
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 mode
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\route.rpt
route
** EQUATIONS **
clk_4Hz : INPUT;
mode : INPUT;
select : INPUT;
set : INPUT;
-- Node name is 'disp_mode0'
-- Equation name is 'disp_mode0', type is output
disp_mode0 = _LC1_A24;
-- Node name is 'disp_mode1'
-- Equation name is 'disp_mode1', type is output
disp_mode1 = _LC2_A16;
-- Node name is ':107' = 'loop10'
-- Equation name is 'loop10', location is LC3_A21, type is buried.
loop10 = DFFE( _EQ001, GLOBAL( clk_4Hz), VCC, VCC, VCC);
_EQ001 = loop11 & set
# !loop10 & set;
-- Node name is ':106' = 'loop11'
-- Equation name is 'loop11', location is LC4_A21, type is buried.
loop11 = DFFE( _EQ002, GLOBAL( clk_4Hz), VCC, VCC, VCC);
_EQ002 = loop11 & set
# loop10 & set;
-- Node name is ':121' = 'num10'
-- Equation name is 'num10', location is LC5_A21, type is buried.
num10 = DFFE( _EQ003, GLOBAL( clk_4Hz), VCC, VCC, VCC);
_EQ003 = loop10 & loop11 & set;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = _LC3_A16;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = _LC1_A16;
-- Node name is 'set_ahr'
-- Equation name is 'set_ahr', type is output
set_ahr = _LC4_A16;
-- Node name is 'set_amin'
-- Equation name is 'set_amin', type is output
set_amin = _LC8_A16;
-- Node name is 'set_day'
-- Equation name is 'set_day', type is output
set_day = _LC3_A24;
-- Node name is 'set_hr'
-- Equation name is 'set_hr', type is output
set_hr = _LC4_A24;
-- Node name is 'set_min'
-- Equation name is 'set_min', type is output
set_min = _LC5_A24;
-- Node name is 'set_mon'
-- Equation name is 'set_mon', type is output
set_mon = _LC6_A16;
-- Node name is 'set_sec'
-- Equation name is 'set_sec', type is output
set_sec = _LC6_A24;
-- Node name is 'set_week'
-- Equation name is 'set_week', type is output
set_week = _LC5_A16;
-- Node name is 'set_year'
-- Equation name is 'set_year', type is output
set_year = _LC2_A24;
-- Node name is ':18'
-- Equation name is '_LC7_A16', type is buried
_LC7_A16 = LCELL( _EQ004);
_EQ004 = _LC1_A24 & _LC2_A16;
-- Node name is ':29'
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = DFFE( _EQ005, GLOBAL( mode), VCC, VCC, VCC);
_EQ005 = !_LC1_A24 & _LC2_A16 & !_LC7_A16
# _LC1_A24 & !_LC2_A16 & !_LC7_A16;
-- Node name is ':30'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = DFFE(!_LC1_A24, GLOBAL( mode), VCC, VCC, VCC);
-- Node name is ':81'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = DFFE( _EQ006, GLOBAL( select), !mode, VCC, VCC);
_EQ006 = _LC1_A16 & !_LC2_A16 & !_LC3_A16
# !_LC1_A16 & !_LC2_A16 & _LC3_A16
# !_LC1_A16 & _LC3_A16 & _LC7_A16
# _LC1_A16 & _LC2_A16 & !_LC7_A16;
-- Node name is ':82'
-- Equation name is '_LC3_A16', type is buried
_LC3_A16 = DFFE( _EQ007, GLOBAL( select), !mode, VCC, VCC);
_EQ007 = _LC1_A16 & !_LC2_A16
# !_LC2_A16 & !_LC3_A16
# _LC2_A16 & _LC3_A16 & !_LC7_A16
# !_LC3_A16 & _LC7_A16;
-- Node name is ':128'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = LCELL( _EQ008);
_EQ008 = clk_4Hz & num10
# !num10 & set;
-- Node name is ':129'
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = LCELL( _EQ009);
_EQ009 = !_LC1_A16 & _LC1_A21 & !_LC1_A24 & _LC3_A16;
-- Node name is '~146~1'
-- Equation name is '~146~1', location is LC1_A21, type is buried.
-- synthesized logic cell
_LC1_A21 = LCELL( _EQ010);
_EQ010 = clk_4Hz & !_LC2_A16 & num10
# !_LC2_A16 & !num10 & set;
-- Node name is ':146'
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = LCELL( _EQ011);
_EQ011 = _LC1_A16 & _LC1_A21 & !_LC1_A24 & !_LC3_A16;
-- Node name is ':163'
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = LCELL( _EQ012);
_EQ012 = _LC1_A16 & _LC1_A21 & !_LC1_A24 & _LC3_A16;
-- Node name is ':179'
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = LCELL( _EQ013);
_EQ013 = !_LC1_A16 & _LC1_A21 & _LC1_A24 & _LC3_A16;
-- Node name is ':196'
-- Equation name is '_LC6_A16', type is buried
_LC6_A16 = LCELL( _EQ014);
_EQ014 = _LC1_A16 & _LC1_A21 & _LC1_A24 & !_LC3_A16;
-- Node name is ':213'
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = LCELL( _EQ015);
_EQ015 = _LC1_A16 & _LC1_A21 & _LC1_A24 & _LC3_A16;
-- Node name is ':226'
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = LCELL( _EQ016);
_EQ016 = !_LC1_A24 & _LC2_A16 & _LC2_A21;
-- Node name is ':243'
-- Equation name is '_LC4_A16', type is buried
_LC4_A16 = LCELL( _EQ017);
_EQ017 = !_LC1_A16 & _LC2_A21 & _LC3_A16 & _LC7_A16;
-- Node name is ':261'
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = LCELL( _EQ018);
_EQ018 = _LC1_A16 & _LC2_A21 & !_LC3_A16 & _LC7_A16;
Project Information e:\amj\eda\experiment\calendar_clock\route.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,145K
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