📄 clkdiv250.rpt
字号:
- 3 - B 09 DFFE + 0 2 0 2 cnt1 (:75)
- 4 - B 09 DFFE + 0 1 0 3 cnt0 (:76)
- 1 - B 11 DFFE + 0 1 1 0 :79
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\clkdiv250.rpt
clkdiv250
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 6/ 48( 12%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\clkdiv250.rpt
clkdiv250
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clki
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\clkdiv250.rpt
clkdiv250
** EQUATIONS **
clki : INPUT;
-- Node name is 'clko'
-- Equation name is 'clko', type is output
clko = _LC1_B11;
-- Node name is ':76' = 'cnt0'
-- Equation name is 'cnt0', location is LC4_B9, type is buried.
cnt0 = DFFE( _EQ001, GLOBAL( clki), VCC, VCC, VCC);
_EQ001 = !cnt0 & _LC2_B6;
-- Node name is ':75' = 'cnt1'
-- Equation name is 'cnt1', location is LC3_B9, type is buried.
cnt1 = DFFE( _EQ002, GLOBAL( clki), VCC, VCC, VCC);
_EQ002 = cnt0 & !cnt1 & _LC2_B6
# !cnt0 & cnt1 & _LC2_B6;
-- Node name is ':74' = 'cnt2'
-- Equation name is 'cnt2', location is LC6_B9, type is buried.
cnt2 = DFFE( _EQ003, GLOBAL( clki), VCC, VCC, VCC);
_EQ003 = cnt2 & _LC2_B6 & !_LC5_B9
# !cnt2 & _LC2_B6 & _LC5_B9;
-- Node name is ':73' = 'cnt3'
-- Equation name is 'cnt3', location is LC2_B9, type is buried.
cnt3 = DFFE( _EQ004, GLOBAL( clki), VCC, VCC, VCC);
_EQ004 = !cnt2 & cnt3 & _LC2_B6
# cnt3 & _LC2_B6 & !_LC5_B9
# cnt2 & !cnt3 & _LC2_B6 & _LC5_B9;
-- Node name is ':72' = 'cnt4'
-- Equation name is 'cnt4', location is LC4_B6, type is buried.
cnt4 = DFFE( _EQ005, GLOBAL( clki), VCC, VCC, VCC);
_EQ005 = cnt4 & _LC2_B6 & !_LC8_B9
# !cnt4 & _LC2_B6 & _LC8_B9;
-- Node name is ':71' = 'cnt5'
-- Equation name is 'cnt5', location is LC5_B6, type is buried.
cnt5 = DFFE( _EQ006, GLOBAL( clki), VCC, VCC, VCC);
_EQ006 = !cnt4 & cnt5 & _LC2_B6
# cnt5 & _LC2_B6 & !_LC8_B9
# cnt4 & !cnt5 & _LC2_B6 & _LC8_B9;
-- Node name is ':70' = 'cnt6'
-- Equation name is 'cnt6', location is LC7_B6, type is buried.
cnt6 = DFFE( _EQ007, GLOBAL( clki), VCC, VCC, VCC);
_EQ007 = cnt6 & _LC2_B6 & !_LC6_B6
# !cnt6 & _LC2_B6 & _LC6_B6;
-- Node name is ':69' = 'cnt7'
-- Equation name is 'cnt7', location is LC1_B6, type is buried.
cnt7 = DFFE( _EQ008, GLOBAL( clki), VCC, VCC, VCC);
_EQ008 = !cnt6 & cnt7 & _LC2_B6
# cnt7 & _LC2_B6 & !_LC6_B6
# cnt6 & !cnt7 & _LC2_B6 & _LC6_B6;
-- Node name is '|lpm_add_sub:80|addcore:adder|:121' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B9', type is buried
_LC5_B9 = LCELL( _EQ009);
_EQ009 = cnt0 & cnt1;
-- Node name is '|lpm_add_sub:80|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = LCELL( _EQ010);
_EQ010 = cnt2 & cnt3 & _LC5_B9;
-- Node name is '|lpm_add_sub:80|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B6', type is buried
_LC6_B6 = LCELL( _EQ011);
_EQ011 = cnt4 & cnt5 & _LC8_B9;
-- Node name is '~12~1'
-- Equation name is '~12~1', location is LC3_B6, type is buried.
-- synthesized logic cell
_LC3_B6 = LCELL( _EQ012);
_EQ012 = !cnt6
# !cnt5
# !cnt4;
-- Node name is ':12'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = LCELL( _EQ013);
_EQ013 = !cnt7
# _LC1_B9
# !cnt3
# _LC3_B6;
-- Node name is ':34'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ014);
_EQ014 = !cnt0 & !cnt1 & !cnt2;
-- Node name is ':79'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = DFFE(!cnt7, GLOBAL( clki), VCC, VCC, VCC);
Project Information e:\amj\eda\experiment\calendar_clock\clkdiv250.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,724K
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