clk_divide_3.fit.eqn

VHDL语言编写三分频

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--temp1 is temp1 at LC_X52_Y12_N6
--operation mode is normal

temp1_lut_out = temp1 $ (!rst & counter1[1]);
temp1 = DFFEAS(temp1_lut_out, GLOBAL(clkin), VCC, , , , , , );


--temp2 is temp2 at LC_X52_Y11_N2
--operation mode is normal

temp2_lut_out = temp2 $ (counter2[1] & !rst);
temp2 = DFFEAS(temp2_lut_out, !GLOBAL(clkin), VCC, , , , , , );


--A1L3 is clkout~0 at LC_X52_Y12_N4
--operation mode is normal

A1L3 = temp2 & (temp1);


--counter1[1] is counter1[1] at LC_X52_Y12_N2
--operation mode is normal

counter1[1]_lut_out = counter1[1] $ (counter1[0] & !rst);
counter1[1] = DFFEAS(counter1[1]_lut_out, GLOBAL(clkin), VCC, , , , , , );


--counter2[1] is counter2[1] at LC_X52_Y11_N4
--operation mode is normal

counter2[1]_lut_out = counter2[1] $ (counter2[0] & !rst);
counter2[1] = DFFEAS(counter2[1]_lut_out, !GLOBAL(clkin), VCC, , , , , , );


--counter1[0] is counter1[0] at LC_X52_Y12_N5
--operation mode is normal

counter1[0]_lut_out = !counter1[0];
counter1[0] = DFFEAS(counter1[0]_lut_out, GLOBAL(clkin), VCC, , !rst, , , , );


--counter2[0] is counter2[0] at LC_X52_Y11_N5
--operation mode is normal

counter2[0]_lut_out = !counter2[0];
counter2[0] = DFFEAS(counter2[0]_lut_out, !GLOBAL(clkin), VCC, , !rst, , , , );


--rst is rst at PIN_L15
--operation mode is input

rst = INPUT();


--clkin is clkin at PIN_J4
--operation mode is input

clkin = INPUT();


--clkout is clkout at PIN_K16
--operation mode is output

clkout = OUTPUT(A1L3);


--t1 is t1 at PIN_K15
--operation mode is output

t1 = OUTPUT(temp1);


--t2 is t2 at PIN_L14
--operation mode is output

t2 = OUTPUT(temp2);