clk_divide_3.tan.qmsg

VHDL语言编写三分频

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clkin register register counter1\[0\] counter1\[1\] 275.03 MHz Internal " "Info: Clock \"clkin\" Internal fmax is restricted to 275.03 MHz between source register \"counter1\[0\]\" and destination register \"counter1\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.123 ns + Longest register register " "Info: + Longest register to register delay is 1.123 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter1\[0\] 1 REG LC_X52_Y12_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y12_N5; Fanout = 2; REG Node = 'counter1\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "" { counter1[0] } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(0.607 ns) 1.123 ns counter1\[1\] 2 REG LC_X52_Y12_N2 2 " "Info: 2: + IC(0.516 ns) + CELL(0.607 ns) = 1.123 ns; Loc. = LC_X52_Y12_N2; Fanout = 2; REG Node = 'counter1\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "1.123 ns" { counter1[0] counter1[1] } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 54.05 % ) " "Info: Total cell delay = 0.607 ns ( 54.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.516 ns ( 45.95 % ) " "Info: Total interconnect delay = 0.516 ns ( 45.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "1.123 ns" { counter1[0] counter1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.123 ns" { counter1[0] counter1[1] } { 0.000ns 0.516ns } { 0.000ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.111 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_J4 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clkin'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "" { clkin } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns counter1\[1\] 2 REG LC_X52_Y12_N2 2 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X52_Y12_N2; Fanout = 2; REG Node = 'counter1\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "1.642 ns" { clkin counter1[1] } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin counter1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 counter1[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 3.111 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_J4 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clkin'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "" { clkin } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns counter1\[0\] 2 REG LC_X52_Y12_N5 2 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X52_Y12_N5; Fanout = 2; REG Node = 'counter1\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "1.642 ns" { clkin counter1[0] } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin counter1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 counter1[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin counter1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 counter1[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin counter1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 counter1[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "1.123 ns" { counter1[0] counter1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.123 ns" { counter1[0] counter1[1] } { 0.000ns 0.516ns } { 0.000ns 0.607ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin counter1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 counter1[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin counter1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 counter1[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "" { counter1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { counter1[1] } {  } {  } } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 29 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "counter1\[0\] rst clkin 4.279 ns register " "Info: tsu for register \"counter1\[0\]\" (data pin = \"rst\", clock pin = \"clkin\") is 4.279 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.353 ns + Longest pin register " "Info: + Longest pin to register delay is 7.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_L15 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_L15; Fanout = 6; PIN Node = 'rst'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "" { rst } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.017 ns) + CELL(0.867 ns) 7.353 ns counter1\[0\] 2 REG LC_X52_Y12_N5 2 " "Info: 2: + IC(5.017 ns) + CELL(0.867 ns) = 7.353 ns; Loc. = LC_X52_Y12_N5; Fanout = 2; REG Node = 'counter1\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "5.884 ns" { rst counter1[0] } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 31.77 % ) " "Info: Total cell delay = 2.336 ns ( 31.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.017 ns ( 68.23 % ) " "Info: Total interconnect delay = 5.017 ns ( 68.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "7.353 ns" { rst counter1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.353 ns" { rst rst~out0 counter1[0] } { 0.000ns 0.000ns 5.017ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.111 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_J4 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clkin'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "" { clkin } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns counter1\[0\] 2 REG LC_X52_Y12_N5 2 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X52_Y12_N5; Fanout = 2; REG Node = 'counter1\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "1.642 ns" { clkin counter1[0] } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin counter1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 counter1[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "7.353 ns" { rst counter1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.353 ns" { rst rst~out0 counter1[0] } { 0.000ns 0.000ns 5.017ns } { 0.000ns 1.469ns 0.867ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin counter1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 counter1[0] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin clkout temp2 8.069 ns register " "Info: tco from clock \"clkin\" to destination pin \"clkout\" through register \"temp2\" is 8.069 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 3.111 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_J4 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clkin'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "" { clkin } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns temp2 2 REG LC_X52_Y11_N2 3 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X52_Y11_N2; Fanout = 3; REG Node = 'temp2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "1.642 ns" { clkin temp2 } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin temp2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 temp2 } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 41 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.734 ns + Longest register pin " "Info: + Longest register to pin delay is 4.734 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp2 1 REG LC_X52_Y11_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y11_N2; Fanout = 3; REG Node = 'temp2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "" { temp2 } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.442 ns) 1.526 ns clkout~0 2 COMB LC_X52_Y12_N4 1 " "Info: 2: + IC(1.084 ns) + CELL(0.442 ns) = 1.526 ns; Loc. = LC_X52_Y12_N4; Fanout = 1; COMB Node = 'clkout~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "1.526 ns" { temp2 clkout~0 } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(2.124 ns) 4.734 ns clkout 3 PIN PIN_K16 0 " "Info: 3: + IC(1.084 ns) + CELL(2.124 ns) = 4.734 ns; Loc. = PIN_K16; Fanout = 0; PIN Node = 'clkout'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.208 ns" { clkout~0 clkout } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.566 ns ( 54.20 % ) " "Info: Total cell delay = 2.566 ns ( 54.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.168 ns ( 45.80 % ) " "Info: Total interconnect delay = 2.168 ns ( 45.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "4.734 ns" { temp2 clkout~0 clkout } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.734 ns" { temp2 clkout~0 clkout } { 0.000ns 1.084ns 1.084ns } { 0.000ns 0.442ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin temp2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 temp2 } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "4.734 ns" { temp2 clkout~0 clkout } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.734 ns" { temp2 clkout~0 clkout } { 0.000ns 1.084ns 1.084ns } { 0.000ns 0.442ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "counter2\[1\] rst clkin -3.248 ns register " "Info: th for register \"counter2\[1\]\" (data pin = \"rst\", clock pin = \"clkin\") is -3.248 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.111 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_J4 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clkin'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "" { clkin } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns counter2\[1\] 2 REG LC_X52_Y11_N4 2 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X52_Y11_N4; Fanout = 2; REG Node = 'counter2\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "1.642 ns" { clkin counter2[1] } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin counter2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 counter2[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 41 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.374 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.374 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_L15 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_L15; Fanout = 6; PIN Node = 'rst'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "" { rst } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.596 ns) + CELL(0.309 ns) 6.374 ns counter2\[1\] 2 REG LC_X52_Y11_N4 2 " "Info: 2: + IC(4.596 ns) + CELL(0.309 ns) = 6.374 ns; Loc. = LC_X52_Y11_N4; Fanout = 2; REG Node = 'counter2\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "4.905 ns" { rst counter2[1] } "NODE_NAME" } "" } } { "clk_divide_3.vhd" "" { Text "E:/Myproject/clk_divide_3/clk_divide_3.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 27.89 % ) " "Info: Total cell delay = 1.778 ns ( 27.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.596 ns ( 72.11 % ) " "Info: Total interconnect delay = 4.596 ns ( 72.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "6.374 ns" { rst counter2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.374 ns" { rst rst~out0 counter2[1] } { 0.000ns 0.000ns 4.596ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "3.111 ns" { clkin counter2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 counter2[1] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clk_divide_3" "UNKNOWN" "V1" "E:/Myproject/clk_divide_3/db/clk_divide_3.quartus_db" { Floorplan "E:/Myproject/clk_divide_3/" "" "6.374 ns" { rst counter2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.374 ns" { rst rst~out0 counter2[1] } { 0.000ns 0.000ns 4.596ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}