clk_divide_3.hier_info

VHDL语言编写三分频

|clk_divide_3
clkin => counter1[0].CLK
clkin => temp1.CLK
clkin => counter1[1].CLK
clkin => counter2[0].CLK
clkin => temp2.CLK
clkin => counter2[1].CLK
rst => counter1[0].ENA
rst => temp1.ENA
rst => counter2[1].ENA
rst => counter2[0].ENA
rst => temp2.ENA
rst => counter1[1].ENA
clkout <= clkout~0.DB_MAX_OUTPUT_PORT_TYPE
t1 <= temp1.DB_MAX_OUTPUT_PORT_TYPE
t2 <= temp2.DB_MAX_OUTPUT_PORT_TYPE