clk_divide_3.tan.rpt

VHDL语言编写三分频

; N/A   ; None         ; 4.279 ns   ; rst  ; counter1[0] ; clkin    ;
; N/A   ; None         ; 4.098 ns   ; rst  ; temp1       ; clkin    ;
; N/A   ; None         ; 3.913 ns   ; rst  ; counter2[0] ; clkin    ;
; N/A   ; None         ; 3.665 ns   ; rst  ; counter1[1] ; clkin    ;
; N/A   ; None         ; 3.302 ns   ; rst  ; temp2       ; clkin    ;
; N/A   ; None         ; 3.300 ns   ; rst  ; counter2[1] ; clkin    ;
+-------+--------------+------------+------+-------------+----------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+-------+--------+------------+
; Slack ; Required tco ; Actual tco ; From  ; To     ; From Clock ;
+-------+--------------+------------+-------+--------+------------+
; N/A   ; None         ; 8.069 ns   ; temp2 ; clkout ; clkin      ;
; N/A   ; None         ; 7.188 ns   ; temp1 ; clkout ; clkin      ;
; N/A   ; None         ; 6.602 ns   ; temp1 ; t1     ; clkin      ;
; N/A   ; None         ; 6.600 ns   ; temp2 ; t2     ; clkin      ;
+-------+--------------+------------+-------+--------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To          ; To Clock ;
+---------------+-------------+-----------+------+-------------+----------+
; N/A           ; None        ; -3.248 ns ; rst  ; counter2[1] ; clkin    ;
; N/A           ; None        ; -3.250 ns ; rst  ; temp2       ; clkin    ;
; N/A           ; None        ; -3.613 ns ; rst  ; counter1[1] ; clkin    ;
; N/A           ; None        ; -3.861 ns ; rst  ; counter2[0] ; clkin    ;
; N/A           ; None        ; -4.046 ns ; rst  ; temp1       ; clkin    ;
; N/A           ; None        ; -4.227 ns ; rst  ; counter1[0] ; clkin    ;
+---------------+-------------+-----------+------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Mar 17 00:48:28 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clk_divide_3 -c clk_divide_3 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkin" is an undefined clock
Info: Clock "clkin" Internal fmax is restricted to 275.03 MHz between source register "counter1[0]" and destination register "counter1[1]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.123 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y12_N5; Fanout = 2; REG Node = 'counter1[0]'
            Info: 2: + IC(0.516 ns) + CELL(0.607 ns) = 1.123 ns; Loc. = LC_X52_Y12_N2; Fanout = 2; REG Node = 'counter1[1]'
            Info: Total cell delay = 0.607 ns ( 54.05 % )
            Info: Total interconnect delay = 0.516 ns ( 45.95 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clkin" to destination register is 3.111 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clkin'
                Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X52_Y12_N2; Fanout = 2; REG Node = 'counter1[1]'
                Info: Total cell delay = 2.180 ns ( 70.07 % )
                Info: Total interconnect delay = 0.931 ns ( 29.93 % )
            Info: - Longest clock path from clock "clkin" to source register is 3.111 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clkin'
                Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X52_Y12_N5; Fanout = 2; REG Node = 'counter1[0]'
                Info: Total cell delay = 2.180 ns ( 70.07 % )
                Info: Total interconnect delay = 0.931 ns ( 29.93 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "counter1[0]" (data pin = "rst", clock pin = "clkin") is 4.279 ns
    Info: + Longest pin to register delay is 7.353 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_L15; Fanout = 6; PIN Node = 'rst'
        Info: 2: + IC(5.017 ns) + CELL(0.867 ns) = 7.353 ns; Loc. = LC_X52_Y12_N5; Fanout = 2; REG Node = 'counter1[0]'
        Info: Total cell delay = 2.336 ns ( 31.77 % )
        Info: Total interconnect delay = 5.017 ns ( 68.23 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clkin" to destination register is 3.111 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clkin'
        Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X52_Y12_N5; Fanout = 2; REG Node = 'counter1[0]'
        Info: Total cell delay = 2.180 ns ( 70.07 % )
        Info: Total interconnect delay = 0.931 ns ( 29.93 % )
Info: tco from clock "clkin" to destination pin "clkout" through register "temp2" is 8.069 ns
    Info: + Longest clock path from clock "clkin" to source register is 3.111 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clkin'
        Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X52_Y11_N2; Fanout = 3; REG Node = 'temp2'
        Info: Total cell delay = 2.180 ns ( 70.07 % )
        Info: Total interconnect delay = 0.931 ns ( 29.93 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.734 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y11_N2; Fanout = 3; REG Node = 'temp2'
        Info: 2: + IC(1.084 ns) + CELL(0.442 ns) = 1.526 ns; Loc. = LC_X52_Y12_N4; Fanout = 1; COMB Node = 'clkout~0'
        Info: 3: + IC(1.084 ns) + CELL(2.124 ns) = 4.734 ns; Loc. = PIN_K16; Fanout = 0; PIN Node = 'clkout'
        Info: Total cell delay = 2.566 ns ( 54.20 % )
        Info: Total interconnect delay = 2.168 ns ( 45.80 % )
Info: th for register "counter2[1]" (data pin = "rst", clock pin = "clkin") is -3.248 ns
    Info: + Longest clock path from clock "clkin" to destination register is 3.111 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J4; Fanout = 6; CLK Node = 'clkin'
        Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X52_Y11_N4; Fanout = 2; REG Node = 'counter2[1]'
        Info: Total cell delay = 2.180 ns ( 70.07 % )
        Info: Total interconnect delay = 0.931 ns ( 29.93 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.374 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_L15; Fanout = 6; PIN Node = 'rst'
        Info: 2: + IC(4.596 ns) + CELL(0.309 ns) = 6.374 ns; Loc. = LC_X52_Y11_N4; Fanout = 2; REG Node = 'counter2[1]'
        Info: Total cell delay = 1.778 ns ( 27.89 % )
        Info: Total interconnect delay = 4.596 ns ( 72.11 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Mar 17 00:48:28 2006
    Info: Elapsed time: 00:00:01