clk_divide_3.tan.summary

VHDL语言编写三分频

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.279 ns
From           : rst
To             : counter1[0]
From Clock     : --
To Clock       : clkin
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.069 ns
From           : temp2
To             : clkout
From Clock     : clkin
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.248 ns
From           : rst
To             : counter2[1]
From Clock     : --
To Clock       : clkin
Failed Paths   : 0

Type           : Clock Setup: 'clkin'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : counter1[0]
To             : counter1[1]
From Clock     : clkin
To Clock       : clkin
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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