unicntr.tan.qmsg

通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register int_reg\[6\] register int_reg\[7\] 113.64 MHz 8.8 ns Internal " "Info: Clock \"clock\" has Internal fmax of 113.64 MHz between source register \"int_reg\[6\]\" and destination register \"int_reg\[7\]\" (period= 8.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.700 ns + Longest register register " "Info: + Longest register to register delay is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_reg\[6\] 1 REG LC14 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg\[6\]'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "" { int_reg[6] } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.100 ns) 4.100 ns Mux~3041 2 COMB SEXP6 1 " "Info: 2: + IC(1.000 ns) + CELL(3.100 ns) = 4.100 ns; Loc. = SEXP6; Fanout = 1; COMB Node = 'Mux~3041'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "4.100 ns" { int_reg[6] Mux~3041 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.600 ns) 6.700 ns int_reg\[7\] 3 REG LC16 10 " "Info: 3: + IC(0.000 ns) + CELL(2.600 ns) = 6.700 ns; Loc. = LC16; Fanout = 10; REG Node = 'int_reg\[7\]'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "2.600 ns" { Mux~3041 int_reg[7] } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns 85.07 % " "Info: Total cell delay = 5.700 ns ( 85.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 14.93 % " "Info: Total interconnect delay = 1.000 ns ( 14.93 % )" {  } {  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "6.700 ns" { int_reg[6] Mux~3041 int_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.700 ns" { int_reg[6] Mux~3041 int_reg[7] } { 0.000ns 1.000ns 0.000ns } { 0.000ns 3.100ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clock 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clock'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "" { clock } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns int_reg\[7\] 2 REG LC16 10 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 10; REG Node = 'int_reg\[7\]'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "0.100 ns" { clock int_reg[7] } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clock 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clock'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "" { clock } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns int_reg\[6\] 2 REG LC14 16 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg\[6\]'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "0.100 ns" { clock int_reg[6] } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "6.700 ns" { int_reg[6] Mux~3041 int_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.700 ns" { int_reg[6] Mux~3041 int_reg[7] } { 0.000ns 1.000ns 0.000ns } { 0.000ns 3.100ns 2.600ns } } } { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "int_reg\[6\] datain\[6\] clock 4.200 ns register " "Info: tsu for register \"int_reg\[6\]\" (data pin = \"datain\[6\]\", clock pin = \"clock\") is 4.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest pin register " "Info: + Longest pin to register delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns datain\[6\] 1 PIN PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; PIN Node = 'datain\[6\]'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "" { datain[6] } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.800 ns Mux~3101 2 COMB LC13 1 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC13; Fanout = 1; COMB Node = 'Mux~3101'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "3.600 ns" { datain[6] Mux~3101 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 4.700 ns int_reg\[6\] 3 REG LC14 16 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 4.700 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg\[6\]'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "0.900 ns" { Mux~3101 int_reg[6] } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns 78.72 % " "Info: Total cell delay = 3.700 ns ( 78.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 21.28 % " "Info: Total interconnect delay = 1.000 ns ( 21.28 % )" {  } {  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "4.700 ns" { datain[6] Mux~3101 int_reg[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.700 ns" { datain[6] datain[6]~out Mux~3101 int_reg[6] } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.200ns 2.600ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clock 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clock'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "" { clock } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns int_reg\[6\] 2 REG LC14 16 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg\[6\]'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "0.100 ns" { clock int_reg[6] } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "4.700 ns" { datain[6] Mux~3101 int_reg[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.700 ns" { datain[6] datain[6]~out Mux~3101 int_reg[6] } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.200ns 2.600ns 0.900ns } } } { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock termcnt int_reg\[6\] 7.400 ns register " "Info: tco from clock \"clock\" to destination pin \"termcnt\" through register \"int_reg\[6\]\" is 7.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clock 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clock'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "" { clock } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns int_reg\[6\] 2 REG LC14 16 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg\[6\]'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "0.100 ns" { clock int_reg[6] } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns + Longest register pin " "Info: + Longest register to pin delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_reg\[6\] 1 REG LC14 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC14; Fanout = 16; REG Node = 'int_reg\[6\]'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "" { int_reg[6] } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.600 ns det_zero~18 2 COMB LC8 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.600 ns; Loc. = LC8; Fanout = 1; COMB Node = 'det_zero~18'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "4.600 ns" { int_reg[6] det_zero~18 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.800 ns termcnt 3 PIN PIN_12 0 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 4.800 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'termcnt'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "0.200 ns" { det_zero~18 termcnt } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 79.17 % " "Info: Total cell delay = 3.800 ns ( 79.17 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 20.83 % " "Info: Total interconnect delay = 1.000 ns ( 20.83 % )" {  } {  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "4.800 ns" { int_reg[6] det_zero~18 termcnt } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.800 ns" { int_reg[6] det_zero~18 termcnt } { 0.000ns 1.000ns 0.000ns } { 0.000ns 3.600ns 0.200ns } } }  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "4.800 ns" { int_reg[6] det_zero~18 termcnt } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.800 ns" { int_reg[6] det_zero~18 termcnt } { 0.000ns 1.000ns 0.000ns } { 0.000ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "int_reg\[7\] serinr clock -0.800 ns register " "Info: th for register \"int_reg\[7\]\" (data pin = \"serinr\", clock pin = \"clock\") is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.300 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clock 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'clock'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "" { clock } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns int_reg\[7\] 2 REG LC16 10 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 10; REG Node = 'int_reg\[7\]'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "0.100 ns" { clock int_reg[7] } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns serinr 1 PIN PIN_26 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_26; Fanout = 1; PIN Node = 'serinr'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "" { serinr } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.800 ns int_reg\[7\] 2 REG LC16 10 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC16; Fanout = 10; REG Node = 'int_reg\[7\]'" {  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "3.600 ns" { serinr int_reg[7] } "NODE_NAME" } "" } } { "../unicntr.vhd" "" { Text "D:/unicntr.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 73.68 % " "Info: Total cell delay = 2.800 ns ( 73.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 26.32 % " "Info: Total interconnect delay = 1.000 ns ( 26.32 % )" {  } {  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "3.800 ns" { serinr int_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.800 ns" { serinr serinr~out int_reg[7] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}  } { { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "1.300 ns" { clock int_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { clock clock~out int_reg[7] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "D:/unicntr/db/unicntr_cmp.qrpt" "" { Report "D:/unicntr/db/unicntr_cmp.qrpt" Compiler "unicntr" "UNKNOWN" "V1" "D:/unicntr/db/unicntr.quartus_db" { Floorplan "D:/unicntr/" "" "3.800 ns" { serinr int_reg[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.800 ns" { serinr serinr~out int_reg[7] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 13 09:27:34 2006 " "Info: Processing ended: Mon Mar 13 09:27:34 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}