44个vhdl实例 注1： 含有不可综合语句

VHDL:Tri-State Buses
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prebus.vhd 


LIBRARY IEEE;
    USE ieee.std_logic_1164.ALL;

ENTITY prebus IS
    PORT(
        my_in  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        sel    : IN STD_LOGIC;
        my_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END prebus;

ARCHITECTURE cpld OF prebus IS
BEGIN
    my_out <= "ZZZZZZZZ"
    WHEN (sel = '1')
    ELSE my_in;
END cpld;