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44个vhdl实例 注1： 含有不可综合语句

-- BCD to Seven Segment Decoder
-- The use of the std_logic literal '-' (don't care) is primarily for the synthesis tool. 
-- This example illustrates the use of the selected signal assignment. 
-- download from: www.pld.com.cn & www.fpga.com.cn


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY seg7dec IS
   PORT(bcdin : IN std_logic_vector(3 DOWNTO 0);
        segout : OUT std_logic_vector(6 DOWNTO 0));
END seg7dec;

ARCHITECTURE ver3 OF seg7dec IS
BEGIN
   WITH bcdin SELECT
      segout <= "1000000" WHEN X"0",
          "1100111" WHEN X"1",

          "1101101" WHEN X"2",
          "0000011" WHEN X"3",
          "0100101" WHEN X"4",
          "0001001" WHEN X"5",
          "0001000" WHEN X"6",
          "1100011" WHEN X"7",
          "0000000" WHEN X"8",
          "0000001" WHEN X"9",
          "-------" WHEN OTHERS;
END ver3;