44个vhdl实例 注1： 含有不可综合语句

-- Latch Inference
-- Download from: http://www.fpga.com.cn

Library IEEE ;
use IEEE.std_logic_1164.all ;

ENTITY latchinf IS
	PORT
	(
		enable, data	: IN BIT;
		q		: OUT BIT
	);
END latchinf;

ARCHITECTURE maxpld OF latchinf IS
BEGIN

latch :	PROCESS (enable, data)
		BEGIN
			IF (enable = '1') THEN
				q <= data;
			END IF;
		END PROCESS latch;

END maxpld;