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44个vhdl实例 注1： 含有不可综合语句

-- Pseudo Random Bit Sequence Generator
-- This design entity uses a single conditional signal assignment statement to describe a PRBSG register. 
-- The length of the register and the two tapping points are defined using generics. 
-- The '&' (aggregate) operator is used to form a vector comprising the shifted contents of the regsiter combined with the XOR feedback which is clocked into the register on the rising edge. 
-- The following Design Entity defeines a parameterised Pseudo-random
-- bit sequence generator, it is useful for generating serial or parallel test waveforms
-- (for paralle waveforms you need to add an extra output port)
-- The generic 'length' is the length of the register minus one.
-- the generics 'tap1' and 'tap2' define the feedabck taps
-- dowload from: www.fpga.com.cn & www.pld.com.cn

library ieee;
use ieee.std_logic_1164.all;

ENTITY prbsgen IS
   GENERIC(length : Positive := 8; tap1 : Positive := 8; tap2 : Positive := 4);
   PORT(clk, reset : IN Bit; prbs : OUT Bit);
END prbsgen;

ARCHITECTURE v2 OF prbsgen IS

   --create a shift register
   SIGNAL prreg : Bit_Vector(length DOWNTO 0);

BEGIN

   --conditional signal assignment shifts register and feeds in xor value
   prreg <= (0 => '1', OTHERS => '0') WHEN reset = '1' ELSE   --set all bits to '0' except lsb
            (prreg((length - 1) DOWNTO 0) & (prreg(tap1) XOR prreg(tap2)))  --shift left with xor feedback
            WHEN clk'EVENT AND clk = '1'
            ELSE prreg;

   --connect msb of register to output
   prbs <= prreg(length);

END v2;