dve_ccir_fir.v

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// -----------------------------------------------------------------------------
//
//
//                  D I G I T A L   C O L O R   V I D E O   E N C O D E R
//       
//                  27 MHZ CCIR601/ITU-R BT-470.3 COMPLIANT
//
// Finite Impulse Response 5-TAP Symmetrical Low Pass Filter
// Version : 2.0
//
// Copyright (c) 1998 Maxim Vlassov ([e-mail])
// 
//
// All rights reserved
//
// Redistribution and reuse of source code and synthesized forms of this source code and it's
// derivatives is strictly permitted under the following conditions:
//
// Redistributions of source code MUST retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions of code in synthesized form MUST reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
//
// Any derivated work from the current design could be not synchronized with the
// latest design updates. Report any design reuse issues to the author.
// Lates release notes and design releases are available upon request via e-mail.
//
// -----------------------------------------------------------------------------
// USER NOTES: Transfer function is hardcoded into the Wallace tree operands:
// Z=X1*0.0625 + X2*0.25 + X3*0.375 + X4*0.25 + X5*0.0625, where
// X1,X2,X3,X4,X5 stand for a_in, b_in, c_in, d_in, e_in
// -----------------------------------------------------------------------------
//
//
// Revision history:
// Version 1.0 from 10/02/1998 - Initical version 
// Verison 1.1 from 01/04/1998 - Production version (minor changes, parametrization added)
// Version 1.2 - 1.9 - slight code optimization for FPGA implementation
// Version 2.0 from 01/01/2002 - NTSC mode / progressive/interlace scan modes implemented
//
//
// -----------------------------------------------------------------------------
//
// 5 operand Wallace tree is implemented
//
// -----------------------------------------------------------------------------
module dve_ccir_fir (
              c_a,
              c_b,
			  c_c,
			  c_d,
			  c_e,
              c_out);
			  
input [7 : 0] c_a,c_b,c_c,c_d,c_e;

output[15 : 0] c_out;

//wire [15 : 0]  c_out;

wire c_c_4_0,c_c_5_0,c_c_5_1,c_c_6_0,c_c_6_1,c_c_6_2,c_c_6_3,c_c_7_0,
     c_c_7_1,c_c_7_2,c_c_7_3,c_c_7_4,c_c_8_0,c_c_8_1,c_c_8_2,c_c_8_3,
     c_c_8_4,c_c_9_0,c_c_9_1,c_c_9_2,c_c_9_3,c_c_9_4,c_c_10_0,c_c_10_1,
     c_c_10_2,c_c_10_3,c_c_10_4,c_c_11_0,c_c_11_1,c_c_11_2,c_c_11_3,c_c_11_4,
     c_c_12_0,c_c_12_1,c_c_12_2,c_c_12_3,c_c_12_4,c_c_13_0,c_c_13_1,c_c_13_2,
     c_c_13_3,c_c_14_0,c_c_14_1,c_c_14_2,c_c_14_3;
     
wire c_o_5_0,c_o_6_0,c_o_6_1,c_o_6_2,c_o_7_0,c_o_7_1,c_o_7_2,c_o_7_3,
     c_o_8_0,c_o_8_1,c_o_8_2,c_o_8_3,c_o_9_0,c_o_9_1,c_o_9_2,
     c_o_9_3,c_o_10_0,c_o_10_1,c_o_10_2,c_o_10_3,c_o_11_0,c_o_11_1,
     c_o_11_2,c_o_11_3,c_o_12_0,c_o_12_1,c_o_12_2,c_o_12_3,c_o_13_0,
     c_o_13_1,c_o_13_2,c_o_14_0,c_o_14_1,c_o_14_2,c_o_15_0,c_o_15_1,c_o_15_2;

// -----------------------------------------------------------------------------
//
// Chrominance filer: Transfer function Z(1)*0.0625 + Z(2)*0.25 + Z(3)*0.375 +
//                                      Z(4)*0.25 + Z(5)*0.0625
// this equals to the following operation:  
//
//       15  14  13  12  11  10  09  08  07  06  05  04  03  02  01  00  
//        0   0   0   0 !ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0  0   0   0   0  
//        0   0   0   0 !ce7 ce6 ce5 ce4 ce3 ce2 ce1 ce0  0   0   0   0 
//        0   0   0 !cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0  0   0   0   0   0
//        0   0 !cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0  0   0   0   0   0   0
//        0   0 !cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0  0   0   0   0   0   0   
//        1   0 !cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0  0   0   0   0   0   0   
// -----------------------------------------------------------------------------
	 
assign c_out[3 : 0] = 4'b0;
//Inputs: c_a[0], c_e[0]
assign c_out[4] = ha(c_a[0],c_e[0]);
assign c_c_4_0  = hc(c_a[0],c_e[0]);
// Inputs: c_a[1],c_e[1],c_c[0],c_c_4_0
assign c_o_5_0  = fa(c_a[1],c_e[1],c_c[0]);
assign c_out[5] = ha(c_o_5_0,c_c_4_0);
assign c_c_5_0  = fc(c_a[1],c_e[1],c_c[0]);
assign c_c_5_1  = hc(c_o_5_0,c_c_4_0);
// Inputs: c_a[2],c_e[2],c_c[1],c_b[0],c_d[0],c_c[0],c_c_5_0,c_c_5_1
assign c_o_6_0  = fa(c_a[2],c_e[2],c_c[1]);
assign c_o_6_1  = ha(c_b[0],c_d[0]);
assign c_o_6_2  = fa(c_o_6_0,c_o_6_1,c_c[0]);
assign c_out[6] = fa(c_o_6_2,c_c_5_0,c_c_5_1);
assign c_c_6_0  = fc(c_a[2],c_e[2],c_c[1]);
assign c_c_6_1  = hc(c_b[0],c_d[0]);
assign c_c_6_2  = fc(c_o_6_0,c_o_6_1,c_c[0]);
assign c_c_6_3  = fc(c_o_6_2,c_c_5_0,c_c_5_1);
// Inputs: c_a[3],c_e[3],c_c[2],c_b[1],c_d[1],c_c[1],c_c_6_0,c_c_6_1,c_c_6_2,c_c_6_3
assign c_o_7_0  = fa(c_a[3],c_e[3],c_c[2]);
assign c_o_7_1  = fa(c_b[1],c_d[1],c_c[1]);
assign c_o_7_2  = ha(c_o_7_0,c_o_7_1);
assign c_o_7_3  = fa(c_c_6_0,c_c_6_1,c_c_6_2);
assign c_out[7] = fa(c_o_7_2,c_o_7_3,c_c_6_3);
assign c_c_7_0  = fc(c_a[3],c_e[3],c_c[2]);
assign c_c_7_1  = fc(c_b[1],c_d[1],c_c[1]);
assign c_c_7_2  = hc(c_o_7_0,c_o_7_1);
assign c_c_7_3  = fc(c_c_6_0,c_c_6_1,c_c_6_2);
assign c_c_7_4  = fc(c_o_7_2,c_o_7_3,c_c_6_3);
// Inputs: c_a[4],c_e[4],c_c[3],c_b[2],c_d[2],c_c[2],c_c_7_0,c_c_7_1,c_c_7_2,c_c_7_3,c_c_7_4,
assign c_o_8_0  = fa(c_a[4],c_e[4],c_c[3]);
assign c_o_8_1  = fa(c_b[2],c_d[2],c_c[2]);
assign c_o_8_2  = fa(c_o_8_0,c_o_8_1,c_c_7_0);
assign c_o_8_3  = fa(c_c_7_1,c_c_7_2,c_c_7_3);
assign c_out[8] = fa(c_o_8_2,c_o_8_3,c_c_7_4);
assign c_c_8_0  = fc(c_a[4],c_e[4],c_c[3]);
assign c_c_8_1  = fc(c_b[2],c_d[2],c_c[2]);
assign c_c_8_2  = fc(c_o_8_0,c_o_8_1,c_c_7_0);
assign c_c_8_3  = fc(c_c_7_1,c_c_7_2,c_c_7_3);
assign c_c_8_4  = fc(c_o_8_2,c_o_8_3,c_c_7_4);
// Inputs: c_a[5],c_e[5],c_c[4],c_b[3],c_d[3],c_c[3],c_c_8_0,c_c_8_1,c_c_8_2,c_c_8_3,c_c_8_4
assign c_o_9_0  = fa(c_a[5],c_e[5],c_c[4]);
assign c_o_9_1  = fa(c_b[3],c_d[3],c_c[3]);
assign c_o_9_2  = fa(c_o_9_0,c_o_9_1,c_c_8_0);
assign c_o_9_3  = fa(c_c_8_1,c_c_8_2,c_c_8_3);
assign c_out[9] = fa(c_o_9_2,c_o_9_3,c_c_8_4);
assign c_c_9_0  = fc(c_a[5],c_e[5],c_c[4]);
assign c_c_9_1  = fc(c_b[3],c_d[3],c_c[3]);
assign c_c_9_2  = fc(c_o_9_0,c_o_9_1,c_c_8_0);
assign c_c_9_3  = fc(c_c_8_1,c_c_8_2,c_c_8_3);
assign c_c_9_4  = fc(c_o_9_2,c_o_9_3,c_c_8_4);
// Inputs: c_a[6],c_e[6],c_c[5],c_b[4],c_d[4],c_c[4],c_c_9_0,c_c_9_1,c_c_9_2,c_c_9_3,c_c_9_4
assign c_o_10_0  = fa(c_a[6],c_e[6],c_c[5]);
assign c_o_10_1  = fa(c_b[4],c_d[4],c_c[4]);
assign c_o_10_2  = fa(c_o_10_0,c_o_10_1,c_c_9_0);
assign c_o_10_3  = fa(c_c_9_1,c_c_9_2,c_c_9_3);
assign c_out[10] = fa(c_o_10_2,c_o_10_3,c_c_9_4);
assign c_c_10_0  = fc(c_a[6],c_e[6],c_c[5]);
assign c_c_10_1  = fc(c_b[4],c_d[4],c_c[4]);
assign c_c_10_2  = fc(c_o_10_0,c_o_10_1,c_c_9_0);
assign c_c_10_3  = fc(c_c_9_1,c_c_9_2,c_c_9_3);
assign c_c_10_4  = fc(c_o_10_2,c_o_10_3,c_c_9_4);

// Inputs: !c_a[7],!c_e[7],c_c[6],c_b[5],c_d[5],c_c[5],c_c_10_0,c_c_10_1,c_c_10_2,c_c_10_3,c_c_10_4
assign c_o_11_0  = fa(c_a[7],c_e[7],c_c[6]);
assign c_o_11_1  = fa(c_b[5],c_d[5],c_c[5]);
assign c_o_11_2  = fa(c_o_11_0,c_o_11_1,c_c_10_0);
assign c_o_11_3  = fa(c_c_10_1,c_c_10_2,c_c_10_3);
assign c_out[11] = fa(c_o_11_2,c_o_11_3,c_c_10_4);
assign c_c_11_0  = ic(c_a[7],c_e[7],c_c[6]);
assign c_c_11_1  = fc(c_b[5],c_d[5],c_c[5]);
assign c_c_11_2  = fc(c_o_11_0,c_o_11_1,c_c_10_0);
assign c_c_11_3  = fc(c_c_10_1,c_c_10_2,c_c_10_3);
assign c_c_11_4  = fc(c_o_11_2,c_o_11_3,c_c_10_4);

// Inputs: !c_c[7],c_b[6],c_d[6],c_c[6],c_c_11_0,c_c_11_1,c_c_11_2,c_c_11_3,c_c_11_4
assign c_o_12_0  = ma(c_c[7],c_b[6],c_d[6]);
assign c_o_12_1  = fa(c_o_12_0,c_c[6],c_c_11_0);
assign c_o_12_2  = fa(c_c_11_1, c_c_11_2,c_c_11_3);
assign c_out[12] = fa(c_o_12_1,c_o_12_2,c_c_11_4);
assign c_c_12_0  = mc(c_c[7],c_b[6],c_d[6]);
assign c_c_12_1  = fc(c_o_12_0,c_c[6],c_c_11_0);
assign c_c_12_2  = fc(c_c_11_1, c_c_11_2,c_c_11_3);
assign c_c_12_3  = fc(c_o_12_1,c_o_12_2,c_c_11_4);

// Inputs: !c_c[7],!c_b[7],!c_d[7],c_c_12_0,c_c_12_1,c_c_12_2,c_c_12_3
assign c_o_13_0  = xa(c_b[7],c_c[7],c_d[7]);
assign c_o_13_1  = fa(c_c_12_0,c_c_12_1,c_c_12_2);
assign c_out[13] = fa(c_o_13_0,c_o_13_1,c_c_12_3);
assign c_c_13_0  = xc(c_b[7],c_c[7],c_d[7]);
assign c_c_13_1  = fc(c_c_12_0,c_c_12_1,c_c_12_2);
assign c_c_13_2  = fc(c_o_13_0,c_o_13_1,c_c_12_3);

// Inputs: c_c_13_0,c_c_13_1,c_c_13_2
assign c_out[14] = fa(c_c_13_0,c_c_13_1,c_c_13_2);
assign c_c_14_0  = fc(c_c_13_0,c_c_13_1,c_c_13_2);

// Inputs: c_a[7],c_b[7],c_c[7],c_d[7],c_e[7],c_c_14_0,c_c_14_1,c_c_14_2,c_c_14_3
assign c_out[15] = ~c_c_14_0;

// -----------------------------------------------------------------------------
//
// Set of basic arithmetic functions
//
// -----------------------------------------------------------------------------
// Full adder function
function fa;
 input a;
 input b;
 input c;
 begin
  fa=a^b^c;
 end
endfunction
// Half adder function
function ha;
 input a;
 input b;
 begin
  ha=a^b;
 end
endfunction
// Full carry generator
function fc;
 input a;
 input b;
 input c;
 begin
  fc=a&b | a&c | b&c;
 end
endfunction
// Half carry generator
function hc;
 input a;
 input b;
 begin
  hc=a&b;
 end
endfunction
// Full carry generator with two inverted inputs
function ic;
 input a;
 input b;
 input c;
 begin
  ic=(~a & ~b) | (~a  | ~b)&c;
 end
endfunction
// Full adder function with one inverted input
function ma;
 input a;
 input b;
 input c;
 begin
  ma=~a^b^c;
 end
endfunction
// Full carry generator with one inverted input
function mc;
 input a;
 input b;
 input c;
 begin
  mc=~a&b | ~a&c | b&c;
 end
endfunction
// Full adder function with all inverted input
function xa;
 input a;
 input b;
 input c;
 begin
  xa=~a^~b^~c;
 end
endfunction
// Full carry generator with all inverted input
function xc;
 input a;
 input b;
 input c;
 begin
  xc=~a&~b | ~a&~c | ~b&~c;
 end
endfunction

endmodule //dve_ccir_fir