dve_ccir_aps.v

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// -----------------------------------------------------------------------------
//
//
//                  D I G I T A L   C O L O R   V I D E O   E N C O D E R
//       
//                  27 MHZ CCIR601/ITU-R BT-470.3 COMPLIANT
//
// ARM Advanced Microcontroller Bus Architecture (AMBA) APB SLAVE INTERFACE
// Version : 2.0
//
// Copyright (c) 1998 Maxim Vlassov ([e-mail])
// 
//
// All rights reserved
//
// Redistribution and reuse of source code and synthesized forms of this source code and it's
// derivatives is strictly permitted under the following conditions:
//
// Redistributions of source code MUST retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions of code in synthesized form MUST reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
//
// Any derivated work from the current design could be not synchronized with the
// latest design updates. Report any design reuse issues to the author.
// Lates release notes and design relseases are available upon request via e-mail.
//
// -----------------------------------------------------------------------------
//
// Revision history:
// Version 1.0 from 10/02/1998 - Initical version 
// Verison 1.1 from 01/04/1998 - Production version (minor changes, parametrization added)
// Version 1.2 - 1.9 - slight code optimization for FPGA implementation
// Version 2.0 from 01/01/2002 - NTSC mode / progressive/interlace scan modes implemented
//
//
// -----------------------------------------------------------------------------
// Implementation requires APB synchronous clock coupled to the sclk. 
// For asynchronous APB implementation use DVE_CCIR_APA.V
module dve_ccir_aps
	(sclk,
         rst_n,
         apb_pstb,
         apb_sel,
         apb_pwrite,
         apb_write,
         apb_read,
         coding_ntsc,
         srst_n,
         color_bars_mode         
	 );
	
// -----------------------------------------------------------------------------
// USER-defined parameters
// -----------------------------------------------------------------------------

// NONE

// -----------------------------------------------------------------------------
// PORTS and INTERNAL RESOURCES declarations
// -----------------------------------------------------------------------------
input                               rst_n;                     // synchronous reset input
input                               sclk;                      // syncronous clock input
                                                               // chip-wide reset (generated by reset controller) 
input                               apb_pstb;                  // 
input                               apb_sel;                   //															   
input                               apb_pwrite;                // flag, which clears the phase
input  [7 : 0]                      apb_write;                 //
output [7 : 0]                      apb_read;                  //
output                              srst_n;                    // synchronous reset output
output                              color_bars_mode;
output                              coding_ntsc;

wire reg_write_ena, reg_read_ena;   // register access decoders
reg                                 reg_mode_change;                     
reg                                 reg_standard_pal;
reg                                 reg_colorbars_mode;
reg                                 reg_mode_vintage;  // delayed mode register
reg                                 reg_reset_output;  // reset output register
// -----------------------------------------------------------------------------
// Mode change, when 1 - loads the NTSC/PAL mode into the mode register,
// resets ASIC
// -----------------------------------------------------------------------------
`define  MODE_REG_RELOAD 0
// -----------------------------------------------------------------------------
// NTSC/PAL STANDARD SELECTOR
// 0 - NTSC-M / 1 PAL-B/G, Reset value - NTSC
// -----------------------------------------------------------------------------
`define MODE_REG_STANDARD 1
// -----------------------------------------------------------------------------
// COLOR BARS ON
// 1 - COLOR BARS / 0 - COLOR BARS OFF
// -----------------------------------------------------------------------------
`define MODE_REG_COLORBARS 2


// -----------------------------------------------------------------------------
// 
// -----------------------------------------------------------------------------
assign reg_write_ena = apb_sel & apb_pstb & apb_pwrite;
assign reg_read_ena  = apb_sel & apb_pstb & ~apb_pwrite;


// 
always @(posedge sclk)
begin
  if (!rst_n)
   begin
    reg_standard_pal<=1'b0;
    reg_mode_change <=1'b1;
   end
  else if (reg_write_ena && apb_write[`MODE_REG_RELOAD])
   begin 
    reg_mode_change <= 1'b1;
    reg_standard_pal<= apb_write[`MODE_REG_STANDARD];
   end
  else
    reg_mode_change <= 1'b0;
end

always @(posedge sclk)
begin
 if (!rst_n)
   reg_colorbars_mode <= 1'b0;
 else if (reg_write_ena)
   reg_colorbars_mode <= apb_write[`MODE_REG_COLORBARS];
end

always @(posedge sclk)
begin
 if (!rst_n)
  begin
   reg_mode_vintage <= 1'b0;
   reg_reset_output <= 1'b0;
  end
 else
  begin
   reg_mode_vintage <= reg_mode_change;
   reg_reset_output <= ~reg_mode_change & reg_mode_vintage;
  end
end

// -----------------------------------------------------------------------------
// Output assignments
// -----------------------------------------------------------------------------
assign srst_n = ~reg_reset_output;
assign coding_ntsc = ~reg_standard_pal;
assign color_bars_mode = reg_colorbars_mode;
assign apb_read = (reg_read_ena) ? {5'b0,reg_colorbars_mode, reg_standard_pal, 1'b0} : 8'b0;
	
endmodule //dve_ccir_aps