dve_ccir_tb.v

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// -----------------------------------------------------------------------------
//
//
//                  D I G I T A L   C O L O R   V I D E O   E N C O D E R
//       
//                  27 MHZ CCIR601/ITU-R BT-470.3 COMPLIANT
//
// DIGITAL VIDEO ENCODER DVE SIGNAL INTEGRITY AND PERFORMANCE DEMONSTRATION TESTBENCH
// Version : 2.0
//
// Copyright (c) 1998 Maxim Vlassov ([e-mail])
// 
//
// All rights reserved
//
// Redistribution and reuse of source code and synthesized forms of this source code and it's
// derivatives is strictly permitted under the following conditions:
//
// Redistributions of source code MUST retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions of code in synthesized form MUST reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
//
// Any derivated work from the current design could be not synchronized with the
// latest design updates. Report any design reuse issues to the author.
// Lates release notes and design relseases are available upon request via e-mail.
//
// -----------------------------------------------------------------------------
//
// Revision history:
// Version 1.0 from 10/02/1998 - Initical version 
// Verison 1.1 from 10/04/1998 - Production version (minor changes, parametrization added)
//
// -----------------------------------------------------------------------------
// USER NOTES: This TESTBENCH suite contains the all necessary code sections
// which can be used to implement the VIDEO PIXEL and CONTROL interfaces in 
// the user host. 
//
// CONFORMANCE TESTBENCH and REGRESSION tests are not available under the listed
// above license agreement.
// Intellectual property of this code and any work based on this code belongs
// to Maxim Vlasov (the Author)
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
module dve_ccir_TB;

// -----------------------------------------------------------------------------
//
// CLOCK frequency declaration and the continuity of the simulation run-time .....
//
// -----------------------------------------------------------------------------
`define CLK_PERIOD       37.037037037037037   // 27 MHz system clock
`define SIMULATION_TIME   10 // 10 us of simulation time
`define PAL_SIMULATION_CYCLES 4324324  //8 fields PAL
`define NTSC_SIMULATION_CYCLES 1837838 //4 fields NTSC
`define RESET_LOW_CYCLES 3      // Number of reset cycles

`define COLORBARS_ON_NTSC 5
`define COLORBARS_ON_PAL  7
`define VIDEO_IN_PAL  3
`define VIDEO_IN_NTSC 1

`define SHORT_SIMULATION_CYCLES  54054


`define PAL_VIDEO_ENABLE			(11'd284 +`PIPELINE_DELAY-11'd1)
`define PAL_VIDEO_DISABLE			(11'd1688+`PIPELINE_DELAY-11'd1)
`define NTSC_VIDEO_ENABLE   (11'd252 +`PIPELINE_DELAY-11'd1) 
`define NTSC_VIDEO_DISABLE			(11'd1674+`PIPELINE_DELAY-11'd1)

// -----------------------------------------------------------------------------
//
//Parameters declaration: 
//
// -----------------------------------------------------------------------------
parameter DEFAULT_TIME = 5;

parameter INPUT_PRECISION = 8;
parameter OUTPUT_PRECISION = 8;
parameter APB_DBUSWIDTH = 8;
// -----------------------------------------------------------------------------
//
//Internal signals declarations:
//
// -----------------------------------------------------------------------------
reg sclk;
reg rst_n;

reg [INPUT_PRECISION-1 : 0] pixel_in;
reg coding_ntsc;
wire hsync_out, vsync_out, csync_out;
wire [OUTPUT_PRECISION-1 : 0] luma_out, chroma_out, fcbs_out;
reg  apb_pstb, apb_sel, apb_pwrite;
reg  [APB_DBUSWIDTH-1 : 0] apb_write;
wire  [APB_DBUSWIDTH-1 : 0] apb_read;
reg pal_coding; // 1 in PAL mode, 0 in NTSC
// -----------------------------------------------------------------------------
//
//SYNCHRONIZATION STATE MACHINE
//
// -----------------------------------------------------------------------------
reg h_sync_vintage;
reg [1 : 0] sync_counter;
`define Y_GATE_0   2'b00 
`define Y_GATE_1   2'b10 
`define CR_GATE  2'b01 
`define CB_GATE  2'b11 
wire y_flag, cr_flag, cb_flag;
wire start_of_line;
reg [INPUT_PRECISION-1 : 0] cr_register, cb_register, y_register;
reg [10 : 0] pel_counter;
wire active_video_enable;
// -----------------------------------------------------------------------------
//
//LOG file declaration.
//
// -----------------------------------------------------------------------------
integer report_file;

// -----------------------------------------------------------------------------
//
//Wait time declaration used in ports monitoring.
//One parameter is declared for every port.
//
// -----------------------------------------------------------------------------
parameter Default_wait_time = 10;
parameter DEFAULT_PROPAGATION   = 1; // 1 ns for FF propagation delay (from sclk to Q)

//Simulation time
parameter SimulationTime = Default_wait_time + `SIMULATION_TIME;

//Errors counter
integer errors_counter;

// -----------------------------------------------------------------------------
//
// TASKS
//
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
// Init all the inputs
// -----------------------------------------------------------------------------
task init_all_inputs;
begin
  pixel_in  = {INPUT_PRECISION{1'b0}};
  apb_pstb = 1'b0;
  apb_sel = 1'b0;
  apb_pwrite = 1'b0;
  apb_write = {APB_DBUSWIDTH{1'b0}};
  pal_coding = 1'b0; // NTSC mode is selected
  
  $display ("Inputs initialized");
 end
endtask // init_all_inputs

// -----------------------------------------------------------------------------
// SET CODING STANDARD TO PAL
// -----------------------------------------------------------------------------
task set_pal;
begin
  @(posedge sclk);
  pal_coding = 1'b1; // PAL mode is selected
  @(posedge sclk);
  $display ("PAL CODING standard is selected");
 end
endtask // init_all_inputs


// -----------------------------------------------------------------------------
// SET CODING STANDARD TO NTSC
// -----------------------------------------------------------------------------
task set_ntsc;
begin
  @(posedge sclk);
  pal_coding = 1'b0; // NTSC mode is selected
  @(posedge sclk);
  $display ("NTSC CODING standard is selected");
 end
endtask // init_all_inputs

// -----------------------------------------------------------------------------
// Init all the inputs
// -----------------------------------------------------------------------------
task write_command_to_dve;
input [APB_DBUSWIDTH-1 : 0] cmd;  // Input command to be written 
begin 			  
  @(posedge sclk);    				
   #(DEFAULT_PROPAGATION); 
   apb_pstb = 1'b0;
   apb_sel = 1'b0;
   apb_pwrite = 1'b0;
   apb_write = {APB_DBUSWIDTH{1'b0}};
  @(posedge sclk);    				
  $display ("Control Word is written");							
  $display ($realtime,,"ps; Written data %b", cmd);
   #(DEFAULT_PROPAGATION); 
   apb_pstb = 1'b1;
   apb_sel = 1'b1;
   apb_pwrite = 1'b1;
   apb_write = cmd;
  @(posedge sclk);    				
   #(DEFAULT_PROPAGATION); 
   apb_pstb = 1'b0;
   apb_sel = 1'b0;
   apb_pwrite = 1'b0;
   apb_write = {APB_DBUSWIDTH{1'b0}};
  @(posedge sclk);    				
   #(DEFAULT_PROPAGATION); 
   apb_pstb = 1'b1;
   apb_sel = 1'b1;
   apb_pwrite = 1'b0;
  @(posedge sclk);    				
   #(DEFAULT_PROPAGATION); 
  $display ($realtime,,"ps; Read back data %b", apb_read);
  @(posedge sclk);    				
   #(DEFAULT_PROPAGATION); 
   apb_pstb = 1'b0;
   apb_sel = 1'b0;
   apb_pwrite = 1'b0;
   apb_write = {APB_DBUSWIDTH{1'b0}};
end
endtask //write_command_to_dve 



// -----------------------------------------------------------------------------
//
// Unit Under Test port map
//
// -----------------------------------------------------------------------------

dve_ccir_top UUT (
                  .sclk(sclk),
                  .rst_n(rst_n),
                  .apb_pstb(apb_pstb),
                  .apb_sel(apb_sel),
                  .apb_pwrite(apb_pwrite),
                  .apb_write(apb_write),
                  .apb_read(apb_read),
                  .pixel_in(pixel_in),
                  .hsync_out(hsync_out),
                  .vsync_out(vsync_out),
                  .csync_out(csync_out),
                  .luma_out(luma_out),
                  .chroma_out(chroma_out),
		  .fcbs_out(fcbs_out)
		);


// -----------------------------------------------------------------------------
//
//
// TB body :
//
//
// -----------------------------------------------------------------------------

initial
	begin: init_fio
	        report_file=$fopen("compare_report.log");
		    errors_counter = 0;
                init_all_inputs;
                @(posedge sclk);
                while (!rst_n)
                
// The datapath check in NTSC mode on the sawtooth signal and color diamonds
    
                                set_ntsc;
				@(posedge sclk);
				repeat (5) @(posedge sclk);
				write_command_to_dve(`VIDEO_IN_NTSC);
				repeat (`SHORT_SIMULATION_CYCLES) @(posedge sclk);

// The datapath check in PAL mode on the sawtooth signal and color diamonds
    
                                set_pal;
				@(posedge sclk);
				repeat (5) @(posedge sclk);
				write_command_to_dve(`VIDEO_IN_PAL);
				repeat (`SHORT_SIMULATION_CYCLES) @(posedge sclk);

// Color bars mode, NTSC, 4 fields				

				@(posedge sclk);
				repeat (5) @(posedge sclk);
				write_command_to_dve(`COLORBARS_ON_NTSC);
				repeat (`NTSC_SIMULATION_CYCLES) @(posedge sclk);
// Color bars mode, PAL, 8 fields				
				repeat (5) @(posedge sclk);
				write_command_to_dve(`COLORBARS_ON_PAL);
				repeat (`PAL_SIMULATION_CYCLES) @(posedge sclk);
	
		if (errors_counter)
		begin
			$display("Errors were encountered, differences are listed in compare_report.log");
			$fdisplay(report_file,"Some vectors failed.");
		end
		else
		begin
			$display("All vectors passed.");
			$fdisplay(report_file,"All vectors passed.");
		end
		$fclose(report_file);
		$stop; //$finish;
	end

// -----------------------------------------------------------------------------
//
// CLOCK generator 
//
// -----------------------------------------------------------------------------
initial
   begin: clock_generator
    sclk = 1'b1;
    forever #(`CLK_PERIOD/2) sclk=~sclk;
   end //clock generator

// -----------------------------------------------------------------------------
//
// Synchronous RESET process 
//
// -----------------------------------------------------------------------------
initial
 begin: reset_process
  rst_n = 1'b0; // Initial value
  repeat (`RESET_LOW_CYCLES) @(posedge sclk); // Insert delay of `RESET_LOW_CYCLES 
  #(DEFAULT_PROPAGATION) rst_n = 1'b1; // Deassert reset
  @(posedge sclk);
 end // reset_process

// -----------------------------------------------------------------------------
//
// Data synchronizer 
// Activates Y/CR/CB gate state machine
//
// -----------------------------------------------------------------------------
always @(posedge sclk)
begin
 if (!rst_n) begin
  h_sync_vintage <= 0;
  sync_counter <= 0;
  end
 else
  begin
   h_sync_vintage <= hsync_out;
   if ((!hsync_out) && (h_sync_vintage))
     sync_counter <= 0;
   else
     sync_counter <= sync_counter + 1;  
  end 
end

assign start_of_line = ~hsync_out & h_sync_vintage;
assign cr_flag = (sync_counter == `CR_GATE) ? 1'b1 : 1'b0;
assign cb_flag = (sync_counter == `CB_GATE) ? 1'b1 : 1'b0;
assign y_flag  = ((sync_counter == `Y_GATE_0) || (sync_counter == `Y_GATE_1)) ? 1'b1 : 1'b0;

// -----------------------------------------------------------------------------
//
// SAWTOOTH GENERATOR 
//
// -----------------------------------------------------------------------------
always @(posedge sclk)
 if (!rst_n) 
  begin
   y_register <= 0;
   pel_counter <= 0;
  end
 else
  begin
    if (start_of_line) 
     begin
      y_register <= 0;
      pel_counter<= 0;
     end 
    else if ((cb_flag) && (active_video_enable) && (y_register!=255)) y_register <= y_register + 1;
    else 
     begin
      pel_counter <= pel_counter + 1;
     end
  end
assign active_video_enable = (((pal_coding) && (pel_counter>`PAL_VIDEO_ENABLE) &&
(pel_counter < `PAL_VIDEO_DISABLE)) || ((!pal_coding) && (pel_counter>`NTSC_VIDEO_ENABLE) &&
(pel_counter < `NTSC_VIDEO_DISABLE))) ?  1'b1 : 1'b0;

always @(posedge sclk)
 if ((!rst_n) || (start_of_line)) 
  begin
   cr_register <= 128;
   cb_register <= 128;
  end
 else
  begin
   if ((cb_flag) && (active_video_enable) && (cr_register != 129)) 
    begin
    cr_register <= cr_register - 1;
    cb_register <= cb_register + 1;
    end
  end
 
// -----------------------------------------------------------------------------
//
// PIXEL DATABUS MULTIPLEXER
//
// -----------------------------------------------------------------------------
always @(y_register, cr_register, cb_register, y_flag, cr_flag, cb_flag)
begin
 if (y_flag)
  pixel_in = y_register;
 else if (cr_flag)
  pixel_in = cr_register;
 else if (cb_flag)
  pixel_in = cb_register;
 else
  pixel_in = 0;
end

endmodule