📄 dve_ccir_dds.v
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// -----------------------------------------------------------------------------
//
//
// D I G I T A L C O L O R V I D E O E N C O D E R
//
// 27 MHZ CCIR601/ITU-R BT-470.3 COMPLIANT
//
// DIRECT DIGITAL SUBCARRIER SYNTHESIZER
// Version : 2.0
//
// Copyright (c) 1998 Maxim Vlassov (maxismsx@hotmail.com)
//
//
// All rights reserved
//
// Redistribution and reuse of source code and synthesized forms of this source code and it's
// derivatives is strictly permitted under the following conditions:
//
// Redistributions of source code MUST retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions of code in synthesized form MUST reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
//
// Any derivated work from the current design could be not synchronized with the
// latest design updates. Report any design reuse issues to the author.
// Lates release notes and design relseases are available upon request via e-mail.
//
// -----------------------------------------------------------------------------
//
// Revision history:
// Version 1.0 from 10/02/1998 - Initical version
// Verison 1.1 from 01/04/1998 - Production version (minor changes, parametrization added)
// Version 1.2 - 1.9 - slight code optimization for FPGA implementation
// Version 2.0 from 01/01/2002 - NTSC mode / progressive/interlace scan modes implemented
//
//
// -----------------------------------------------------------------------------
// Operation principle: !!! BURST sine is not stored in the look-up table !!!
// It is computed as an ordinary UV data on-fly
//
//
module dve_ccir_dds
(sclk,
srst_n,
coding_ntsc,
set_phase_flag,
frame_number,
end_of_line_flag,
fsc_tbl_addr
);
// -----------------------------------------------------------------------------
// USER-defined parameters
// -----------------------------------------------------------------------------
parameter SUBCARRIER_FRACTION_PRECISION = 21;
parameter SUBCARRIER_INTEGER_PRECISION = 11;
parameter SUBCARRIER_PRECISION=SUBCARRIER_FRACTION_PRECISION+SUBCARRIER_INTEGER_PRECISION;
// -----------------------------------------------------------------------------
// PORTS and INTERNAL RESOURCES declarations
// -----------------------------------------------------------------------------
input sclk; // 27.000 MHz synchronous clock input
// DDS subcarrier generation:
// PAL mode: Fsc = 4.43361875 MHz
// NTSC mode: Fsc = 3.579545 MHz
input srst_n; // synchronous, active low,
// chip-wide reset (generated by reset controller)
input coding_ntsc; // when 1, NTSC is activated
input set_phase_flag; // flag, which clears the phase
input [1 : 0] frame_number; // current frame number
input end_of_line_flag; // Enables the computation of the next
// initial phase
output [SUBCARRIER_INTEGER_PRECISION-1 : 0] fsc_tbl_addr; // Integer phase output
// -----------------------------------------------------------------------------
// SOME CONSTANT declarations
// -----------------------------------------------------------------------------
`define NTSC_PHASE_INCREMENT 32'd569408543
`define PAL_PHASE_INCREMENT 32'd705268427
`define CURRENT_FRAME_0 2'd0
`define CURRENT_FRAME_1 2'd1
`define CURRENT_FRAME_2 2'd2
`define CURRENT_FRAME_3 2'd3
`define NTSC_LINE_INCREMENT 32'h80000000
`define PAL_LINE_INCREMENT 32'd3228097420
`define INITIAL_PHASE_0 32'h0
`define INITIAL_PHASE_90 32'h40000000
`define INITIAL_PHASE_180 32'h80000000
`define INITIAL_PHASE_270 32'hC0000000
// -----------------------------------------------------------------------------
reg [SUBCARRIER_PRECISION-1 : 0] subc_phase_accumulator; //Subcarrier phase accumulator
reg [SUBCARRIER_PRECISION-1 : 0] debut_phase_calculator; // Computes the initial FSC phase
// for the beging of every scan line
//
reg cmd_calculate_reg; // calculate next phase command
wire [SUBCARRIER_PRECISION-1 : 0] subc_phase_increment; //
wire [SUBCARRIER_PRECISION-1 : 0] phase_line_increment;
reg [SUBCARRIER_PRECISION-1 : 0] initial_phase_value;
// -----------------------------------------------------------------------------
// Phase accumulator declaration and a phase temporary storage
// -----------------------------------------------------------------------------
always @(posedge sclk)
begin
if (~srst_n)
subc_phase_accumulator <= {SUBCARRIER_PRECISION{1'b0}};//repeat SUBCARRIER_PRECISION times
else if (set_phase_flag)
subc_phase_accumulator <= initial_phase_value;
else if (end_of_line_flag)
subc_phase_accumulator <= debut_phase_calculator;
else
subc_phase_accumulator<= subc_phase_accumulator + subc_phase_increment;
end
// -----------------------------------------------------------------------------
// Initial phase accumulator
// -----------------------------------------------------------------------------
always @(posedge sclk)
begin
if (~srst_n)
debut_phase_calculator <= {SUBCARRIER_PRECISION{1'b0}};
else if (set_phase_flag)
debut_phase_calculator <= initial_phase_value;
else if (cmd_calculate_reg)
debut_phase_calculator <= debut_phase_calculator + phase_line_increment;
end
// -----------------------------------------------------------------------------
// For PAL the phase shift for every
// single line is 270.576 degrees, for NTSC exactly 180 degrees
// -----------------------------------------------------------------------------
assign phase_line_increment = (coding_ntsc) ? `NTSC_LINE_INCREMENT : `PAL_LINE_INCREMENT;
always @(frame_number or coding_ntsc)
case (frame_number)
`CURRENT_FRAME_0 : begin
if (coding_ntsc)
initial_phase_value = `INITIAL_PHASE_180;
else
initial_phase_value = `INITIAL_PHASE_270;
end
`CURRENT_FRAME_1 : begin
if (coding_ntsc)
initial_phase_value = `INITIAL_PHASE_0;
else
initial_phase_value = `INITIAL_PHASE_180;
end
`CURRENT_FRAME_2 : begin
if (coding_ntsc)
initial_phase_value = `INITIAL_PHASE_180;
else
initial_phase_value = `INITIAL_PHASE_90;
end
`CURRENT_FRAME_3 : initial_phase_value = `INITIAL_PHASE_0;
endcase
// -----------------------------------------------------------------------------
// FSC PAL/NTSC frequency switch
// -----------------------------------------------------------------------------
//
assign subc_phase_increment = (coding_ntsc) ? `NTSC_PHASE_INCREMENT : `PAL_PHASE_INCREMENT;
// -----------------------------------------------------------------------------
// Initial phase loader
// -----------------------------------------------------------------------------
always @(posedge sclk)
if (~srst_n) cmd_calculate_reg <= 1'b1;
else cmd_calculate_reg <= end_of_line_flag;
// -----------------------------------------------------------------------------
// Output assignments
// -----------------------------------------------------------------------------
assign fsc_tbl_addr = subc_phase_accumulator[SUBCARRIER_PRECISION-1 : SUBCARRIER_FRACTION_PRECISION];
endmodule //dve_ccir_dds
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