dve_ccir_dph.v

全电视信号编码器

// -----------------------------------------------------------------------------
//
// COLOR BARS SERIALIZER
//
// -----------------------------------------------------------------------------
assign  colorbars_mux= {INPUT_PRECISION{y_gate}}&y_bars |
{INPUT_PRECISION{cb_gate}}&u_bars | 
{INPUT_PRECISION{cr_gate}}&v_bars;

// -----------------------------------------------------------------------------
//
// INPUT VIDEO LIMITER/SIGNAL CONDITIONER
// Does not change representation of Y value, however CR/CB converted
// from UNSIGNED to SIGNED format
// -----------------------------------------------------------------------------

assign videosource_mux = (color_bars_mode) ? colorbars_mux : pixel_in;

always @(y_gate or cr_gate or cb_gate or videosource_mux)
begin
	if (y_gate)
	 begin
		if      (videosource_mux<`Y_LOWBOUNDARY)
			video_limiter = `Y_BLACK_LEVEL^8'd128;
		else if (videosource_mux>`Y_HIGHBOUNDARY)
			video_limiter = `Y_WHITE_LEVEL^8'd128;
		else video_limiter={~videosource_mux[INPUT_PRECISION-1],videosource_mux[INPUT_PRECISION-2 : 0]};
	 end
	else if (cr_gate | cb_gate)
// This fork is active, when CR or CB gates are asserted
	 begin
		if (videosource_mux < `CRCB_LOWBOUNDARY)
		 video_limiter = `CRCB_LOWBOUNDARY^8'h80;
		else if (videosource_mux > `CRCB_HIGHBOUNDARY)
		 video_limiter = `CRCB_HIGHBOUNDARY^8'h80;
		else video_limiter={~videosource_mux[INPUT_PRECISION-1],videosource_mux[INPUT_PRECISION-2 : 0]};
	 end
        else
         video_limiter = 8'd128;
end	

// -----------------------------------------------------------------------------
//
// CLAMPED VIDEO AND COLOR BARS INTERMEDIATE REGISTER
// 
// The following sequence is applied: Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, .....
// -----------------------------------------------------------------------------
always @(posedge sclk)
	 cvideo_reg <= video_limiter;

// -----------------------------------------------------------------------------
//
// Table with scaling coefficients:
// In PAL mode, in order to vary the V flag polarity, 
// the sign of the scaling factor coefficient is changed in respect to V
// flag polarity
//
// -----------------------------------------------------------------------------
always @(coding_ntsc or y_gate or cr_gate or cb_gate)
begin
 if (coding_ntsc)							   
  begin
// NTSC coding fork. Simply according to y/cr/cb flags present the scaling factor   		 
   if (y_gate)
	scaling_mux=`Y_SCALE_NTSC;
   else if (cr_gate)
	scaling_mux=`V_SCALE_NTSC;
   else if (cb_gate)
	scaling_mux=`U_SCALE_NTSC;
   else scaling_mux=9'b0;
  end
 else
  begin
   if (y_gate)
    scaling_mux=`Y_SCALE_PAL;
   else if (cb_gate)
    scaling_mux=`U_SCALE_PAL;
   else if (cr_gate)
    scaling_mux=`V_SCALE_PAL;
   else scaling_mux=9'b0;
  end
 end	
	
// -----------------------------------------------------------------------------
//
// SCALING FACTOR INTERMEDIATE REGISTER
// 
// -----------------------------------------------------------------------------
always @(posedge sclk)
 if (~srst_n) scaling_reg<=9'd0;
 else scaling_reg<=scaling_mux;
	
	
// -----------------------------------------------------------------------------
//
// SCALING MULTIPLIER
// 
// -----------------------------------------------------------------------------
dve_ccir_mlt8x9 prescaler (.sclk(sclk),
                          .srst_n(srst_n),
                          .a_in(cvideo_reg),
                          .b_in(scaling_reg),
		          .p_out(scaled_data));

// -----------------------------------------------------------------------------
//
// ..... Pipeline control signals .....
//
// -----------------------------------------------------------------------------
always @(posedge sclk)
 begin
  if (!srst_n)
   begin 
    y_gate_delayed <= 1'b0;
	u_gate_delayed <= 1'b0;
	v_gate_delayed <= 1'b0;
	y_gate_dbldel  <= 1'b0;
	u_gate_dbldel  <= 1'b0;
	v_gate_dbldel  <= 1'b0;
   end
  else
   begin
	y_gate_delayed <= y_gate;
	u_gate_delayed <= cb_gate;
	v_gate_delayed <= cr_gate;
	y_gate_dbldel  <= y_gate_delayed;
	u_gate_dbldel  <= u_gate_delayed;
	v_gate_dbldel  <= v_gate_delayed;
   end
end

// -----------------------------------------------------------------------------
//
// Scaled Y and UV data registers. Store the results of multiplication
// 
// -----------------------------------------------------------------------------
always @(posedge sclk)
begin
 if (y_gate_delayed)
  y_scaled_reg <= scaled_data;	
  y_fir_tap_0_reg <= y_biased_mux;
  y_fir_tap_1_reg <= y_fir_tap_0_reg;
  y_fir_tap_2_reg <= y_fir_tap_1_reg;
end

assign y_bias_mux = (coding_ntsc) ? `Y_NTSC_SCALED_BIAS : `Y_PAL_SCALED_BIAS;
assign y_biased_mux = {~y_scaled_reg[15],y_scaled_reg[14 : 0]} - y_bias_mux;

// -----------------------------------------------------------------------------
//
// ..... Luminance sync insertion .....
// 
// -----------------------------------------------------------------------------
always @(sync_levels or coding_ntsc)
begin
 case (sync_levels)
 `SYNC_ADR_BLANK   : begin
                     if (coding_ntsc)
                      sync_mux <= `NTSC_SYNC_BLANK;
                     else
                      sync_mux <= `PAL_SYNC_BLANK;
                     end
 `SYNC_ADR_LEADER  : begin
                     if (coding_ntsc)
                      sync_mux <= `NTSC_SYNC_LEADER;
                     else
                      sync_mux <= `PAL_SYNC_LEADER;
                     end
 `SYNC_ADR_ZEROH   : begin
                     if (coding_ntsc)
                      sync_mux <= `NTSC_SYNC_ZEROH;
                     else
                      sync_mux <= `PAL_SYNC_ZEROH;
                     end
 `SYNC_ADR_TRAILER : begin
                     if (coding_ntsc)
                      sync_mux <= `NTSC_SYNC_TRAILER;
                     else
                      sync_mux <= `PAL_SYNC_TRAILER;
                     end
 `SYNC_ADR_TIP     : begin
                     if (coding_ntsc)
                      sync_mux <= `NTSC_SYNC_TIP;
                     else
                      sync_mux <= `PAL_SYNC_TIP;
                     end
 default : begin
                     if (coding_ntsc)
                      sync_mux <= `NTSC_BLACK_LEVEL;
                     else
                      sync_mux <= `PAL_BLACK_LEVEL;
                     end
 endcase
end

// -----------------------------------------------------------------------------
//
// LUMINANCE FIR 3-TAP SUMM OF PRODUCTS matrix
// !!! Arguments are UNSIGNED INTEGER VALUES !!! 
// -----------------------------------------------------------------------------
assign y_fir_output= add_quarta_halfb_quartc(y_fir_tap_0_reg, y_fir_tap_1_reg, y_fir_tap_2_reg);

always @(posedge sclk)
begin
 if (y_gate_delayed)
 begin
  if (video_enable)
   y_fir_reg <=y_fir_output[15 : 5];
  else
   y_fir_reg <= sync_mux;   
  
   y_fir_del_reg <= y_fir_reg;
  end
end

assign bilinear_converter_out = range_halfa_halfb(y_fir_reg, y_fir_del_reg);

assign y_oversampler_out = (y_gate_delayed) ? bilinear_converter_out[15 : 5] : y_fir_del_reg;

always @(posedge sclk)
begin
 y_oversampler_reg <= y_oversampler_out[10 : 11-OUTPUT_PRECISION];
 y_pipeadj_reg <= y_oversampler_reg;
 luma_reg   <= y_pipeadj_reg;
end

always @(posedge sclk)
begin
 if (u_gate_delayed | v_gate_delayed)
  uv_scaled_reg <= scaled_data[15 : 8];	 
end

// -----------------------------------------------------------------------------
//
// CHROMA FIR registered pipeline
// 
// -----------------------------------------------------------------------------
always @(posedge sclk)
begin
// if (u_gate_dbldel | v_gate_dbldel)
// Modification from 30.03.2003
  if (u_gate_delayed | v_gate_delayed)
  begin
   stage_bu_reg <= uv_scaled_reg;
   stage_bv_reg <= stage_bu_reg;
   stage_cu_reg <= stage_bv_reg;
   stage_cv_reg <= stage_cu_reg;
   stage_du_reg <= stage_cv_reg;
   stage_dv_reg <= stage_du_reg;
   stage_eu_reg <= stage_dv_reg;
   stage_ev_reg <= stage_eu_reg;
  end
 end	 
	 
// -----------------------------------------------------------------------------
//
// CHROMA FIR 5-TAP SUMM OF PRODUCTS matrix
// 
// -----------------------------------------------------------------------------
dve_ccir_fir CHROMA_FIR ( .c_a(uv_scaled_reg),
			  .c_b(stage_bv_reg),
			  .c_c(stage_cv_reg),
			  .c_d(stage_dv_reg),
			  .c_e(stage_ev_reg),
			  .c_out(chroma_filtered));
	
// -----------------------------------------------------------------------------
//
// Aligning stage and interpolation logic
// 
// -----------------------------------------------------------------------------
always @(posedge sclk)
begin
 if (v_gate_dbldel)
  begin
   storage_v_reg <= chroma_filtered[15:8];  // stores the output of filter V0
   vintage_v_reg <= storage_v_reg;	 // V-1 sample for 4x interpolator 
   storage_u_reg <= retimed_u_reg;    // U0  sample storage
   vintage_u_reg <= storage_u_reg;    // U-1 sample for 4x interpolator
  end
 end	 

always @(posedge sclk)
begin
 if (v_gate_delayed)
  retimed_u_reg<= chroma_filtered[15:8];  // stores the output of filter U0
end			  

// -----------------------------------------------------------------------------
//
// Time slot 4x oversampling counter
//
// -----------------------------------------------------------------------------
always @(posedge sclk)
begin
	if (!srst_n | v_gate_delayed) oversampling_counter<=2'b0;
	else 
	 case (oversampling_counter)
		 2'b00 : oversampling_counter <= 2'b11;
		 2'b01 : oversampling_counter <= 2'b00;
		 2'b10 : oversampling_counter <= 2'b01;
		 2'b11 : oversampling_counter <= 2'b10;
	 endcase
end		
			  
// -----------------------------------------------------------------------------
//
// U/V oversampling multiplexer
//
// -----------------------------------------------------------------------------

always @(oversampling_counter or storage_u_reg or vintage_u_reg or storage_v_reg or vintage_v_reg)
begin
 case (oversampling_counter)
  2'b11 : begin 
	       u_oversampling_mux = {vintage_u_reg,8'b0};
               v_oversampling_mux = {vintage_v_reg,8'b0};
	  end
  2'b10 : begin 
	       u_oversampling_mux = add_threea_quartb(vintage_u_reg,storage_u_reg);
  		   v_oversampling_mux = add_threea_quartb(vintage_v_reg,storage_v_reg);
  	  end
  2'b01 : begin 
	       u_oversampling_mux = add_halfa_halfb (storage_u_reg, vintage_u_reg);
           v_oversampling_mux = add_halfa_halfb (storage_v_reg, vintage_v_reg);
		  end
  
  2'b00 : begin
	       u_oversampling_mux = add_threea_quartb(storage_u_reg, vintage_u_reg);
           v_oversampling_mux = add_threea_quartb(storage_v_reg, vintage_v_reg);
          end 
  endcase
end

assign u_color_burst_mux = (coding_ntsc) ? `U_BURST_NTSC : `U_BURST_PAL;
assign v_color_burst_mux = (coding_ntsc) ? `V_BURST_NTSC : `V_BURST_PAL;

// -----------------------------------------------------------------------------
//
// CODE CONFIGURATION FORK FOLLOWS BELOW
//
// -----------------------------------------------------------------------------
`ifdef DEBUG_QUADRATURE
 always @(u_color_burst_mux or v_color_burst_mux or u_oversampling_mux or v_oversampling_mux or 
 burst_gate or video_enable)
 begin
  case ({burst_gate, video_enable})
  2'b01 : begin
          u_conditioned_out = 8'd127;
          v_conditioned_out = 8'd0;
         end
  default : begin
          u_conditioned_out = u_color_burst_mux;
          v_conditioned_out = v_color_burst_mux;
         end
  endcase
 end
`else
 always @(u_color_burst_mux or v_color_burst_mux or u_oversampling_mux or v_oversampling_mux or 
 burst_gate or video_enable)
 begin
  case ({burst_gate, video_enable})
  2'b10  : begin
          u_conditioned_out = u_color_burst_mux;
          v_conditioned_out = v_color_burst_mux;
         end
          
  2'b01 : begin
          u_conditioned_out = u_oversampling_mux[15 : 8];
          v_conditioned_out = v_oversampling_mux[15 : 8];
         end
  default : begin
           u_conditioned_out = 8'd0;
           v_conditioned_out = 8'd0;
          end
  endcase
 end
`endif

always @(posedge sclk)
begin
 u_oversampling_reg <= u_conditioned_out; //
 v_oversampling_reg <= v_conditioned_out; //	
end
	
// -----------------------------------------------------------------------------
//
// QUADRATURE MODULATOR 
//
// -----------------------------------------------------------------------------