📄 dve_ccir_dph.v
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// -----------------------------------------------------------------------------
//
//
// D I G I T A L C O L O R V I D E O E N C O D E R
//
// Video datapath
// Version : 1.0
//
// Copyright (c) 1998 Maxim Vlassov (maxismsx@hotmail.com)
//
// All rights reserved
//
// Redistribution and reuse of source code and synthesized forms of this source code and it's
// derivatives is strictly permitted under the following conditions:
//
// Redistributions of source code MUST retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions of code in synthesized form MUST reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
//
// Any derivated work from the current design could be not synchronized with the
// latest design updates. Report any design reuse issues to the author.
// Lates release notes and design relseases are available upon request via e-mail.
//
// -----------------------------------------------------------------------------
//
// Video data path
// Input Y/CR/CB data is limited to valid values, scaled, filtered, interpolated
// and modulated
//
// -----------------------------------------------------------------------------
module dve_ccir_dph ( sclk,
srst_n,
pixel_in,
y_gate,
cb_gate,
cr_gate,
coding_ntsc,
sync_levels,
burst_gate,
video_enable,
pal_v_flag,
color_bars_mode,
color_bars,
fsc_tbl_addr,
luma_out,
chroma_out,
fcbs_out
);
`undef DEBUG_QUADRATURE
`undef SIGNED_DAC_STAGE
// -----------------------------------------------------------------------------
// USER-defined parameters
// -----------------------------------------------------------------------------
parameter INPUT_PRECISION = 8;
parameter OUTPUT_PRECISION = 8;
parameter DATAPATH_WIDTH = 16;
parameter SYNC_LEVELS_NUMBER=3;
parameter MULT_WIDTH=DATAPATH_WIDTH>>1;
parameter SUBCARRIER_INTEGER_PRECISION = 11;
// Enables 8 bit modulator configuration and look-up table
//`define MODULATOR_CONFIGURATION_8BIT
// Enables 9 bit modulator configuration and look-up table
`define MODULATOR_CONFIGURATION_9BIT
// Enables the SIGNED DAC output stage option
//`define SIGNED_DAC_STAGE
// Uncomment this line to enable the QAM modulator debug mode option
//`define DEBUG_QUADRATURE
// -----------------------------------------------------------------------------
// END OF USER DEFINED PARAMETERS
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
// Check and prepare the USER-DEFINED QUADRATURE MULTIPLIER DATAPATH CONFIGURATION
// -----------------------------------------------------------------------------
`ifdef MODULATOR_CONFIGURATION_8BIT
`undef MODULATOR_CONFIGURATION_9BIT
`else
`define MODULATOR_CONFIGURATION_9BIT
`endif
input sclk; // synchronous pixel clock input (4Fsc)
// 27.000000 MHz clock
//
input srst_n; // synchronous, active low,
// chip-wide reset (generated by reset controller)
input [INPUT_PRECISION-1 : 0] pixel_in; // Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 multiplex
input y_gate;
input cr_gate;
input cb_gate;
input coding_ntsc; // when 1 - NTSC, 0 - PAL
input [SYNC_LEVELS_NUMBER-1 : 0] sync_levels; //
input video_enable; // Tells to the multiplexer to take the sync value
input burst_gate;
input color_bars_mode; // When 1, selects color bars
input [2 : 0] color_bars;
input pal_v_flag;
input [SUBCARRIER_INTEGER_PRECISION-1 : 0] fsc_tbl_addr; // Integer phase, look-up table direct address
output [OUTPUT_PRECISION-1 : 0] luma_out;
output [OUTPUT_PRECISION-1 : 0] chroma_out;
output [OUTPUT_PRECISION-1 : 0] fcbs_out;
reg [INPUT_PRECISION-1 : 0] y_bars,u_bars,v_bars; // Bars color selector
wire [INPUT_PRECISION-1 : 0] colorbars_mux; // Bars video multiplexer
wire [INPUT_PRECISION-1 : 0] videosource_mux; // Video mixing multiplexer
reg [INPUT_PRECISION-1 : 0] video_limiter; // video clipping logic
reg [INPUT_PRECISION-1 : 0] cvideo_reg; // Multicomponent register
reg [INPUT_PRECISION : 0] scaling_mux; // multiplexer for scale factors
reg [INPUT_PRECISION : 0] scaling_reg; // Temporary register to store scaling coefficient
wire [15 : 0] scaled_data; // scaled Y/U/V data
wire [15 : 0] y_bias_mux; // bias level selector
wire [15 : 0] y_biased_mux; // Signed to Unsigned natural number correction
reg [15 : 0] y_scaled_reg; // scaled data register
reg [7 : 0] uv_scaled_reg; // scaled data register
reg y_gate_delayed; // delayed for 1 cycle y_gate
reg u_gate_delayed; // delayed for 1 cycle cb_gate
reg v_gate_delayed; // delayed for 1 cycle cr_gate
reg y_gate_dbldel; // y_gate delayed for 2 cycles
reg u_gate_dbldel; // cb_gate delayed for 2 cycles
reg v_gate_dbldel; // cr_gate delayed for 2 cycles
reg [7 : 0] stage_bu_reg, stage_bv_reg; // second stage of FIR the filter
reg [7 : 0] stage_cu_reg, stage_cv_reg; // third stage of FIR filter
reg [7 : 0] stage_du_reg, stage_dv_reg; // fourth stage of FIR filter
reg [7 : 0] stage_eu_reg, stage_ev_reg; // stage no 5 of FIR filter
wire [15 : 0] chroma_filtered; // Output of FIR filter
// Chroma 4x oversampling and time realignning registers
reg [7 : 0] storage_v_reg,storage_u_reg,vintage_v_reg,vintage_u_reg,retimed_u_reg;
reg [1 : 0] oversampling_counter;
wire [7 : 0] u_color_burst_mux; // sets the U and V or I and Q levels in respect to the burst
wire [7 : 0] v_color_burst_mux; // sets the U and V or I and Q levels in respect to the burst
reg [7 : 0] u_oversampling_reg,v_oversampling_reg; // U/V 4x oversampling registers
reg [15 : 0] u_oversampling_mux, v_oversampling_mux; // U/V 4x commutator/linear interpolator
reg [7 : 0] u_conditioned_out; // BURST insertion/blanking U axe multiplexer
reg [7 : 0] v_conditioned_out; // BURST insertion/blanking V axe multiplexer
wire quadrature_axe; // Output of comparator, which shows, that
// the current phase equals 0/45/90/135....
wire [SUBCARRIER_INTEGER_PRECISION-4 : 0] lut_adr_mux;
reg negate_u_product, negate_v_product, bypass_v_component, bypass_u_component;
reg negate_u_reg, bypass_u_reg, negate_v_reg, bypass_v_reg;
// -----------------------------------------------------------------------------
// Conditional modulator configuration
// -----------------------------------------------------------------------------
`ifdef MODULATOR_CONFIGURATION_8BIT
// Select 8 bit quadrature arguments
reg [6 : 0] sin_wt_reg,cos_wt_reg;
wire [6 : 0] lut_cos_out, lut_sin_out;
reg [6 : 0] sin_wt_mux, cos_wt_mux;
wire [14 : 0] u_by_sin_wt_out, v_by_cos_wt_out;
`else
// Select 9 bit quadrature arguments
reg [7 : 0] sin_wt_reg,cos_wt_reg;
wire [7 : 0] lut_cos_out, lut_sin_out;
reg [7 : 0] sin_wt_mux, cos_wt_mux;
wire [15 : 0] u_by_sin_wt_out, v_by_cos_wt_out;
`endif
reg negate_del_u_reg, negate_del_v_reg, bypass_del_u_reg, bypass_del_v_reg;
reg [15 : 0] u_by_sin_wt_reg, v_by_cos_wt_reg; // stores the result of multiplication
reg [7 : 0] u_bypass_reg, v_bypass_reg; // bypasses the content of u/v_oversampling_reg
wire [15 : 0] u_by_sin_wt_final, v_by_cos_wt_final;
reg [15 : 0] chroma_adder_out; // output of the chrominance signal
// two's complement output
reg [10 : 0] sync_mux; // sync multiplexer
reg [15 : 0] y_fir_tap_0_reg; // FIR filter runs with full scale resolution
reg [15 : 0] y_fir_tap_1_reg; // in order to avoid possible losses of quality
reg [15 : 0] y_fir_tap_2_reg; // and luminance linearity due to the LSB data truncation
wire[15 : 0] y_fir_output; //
reg [10 : 0] y_fir_reg; // output of the Y 3-tap LPF
reg [10 : 0] y_fir_del_reg; // output of the Y 3-tap LPF
wire [15 : 0] bilinear_converter_out;
wire [10 : 0] y_oversampler_out;
reg [OUTPUT_PRECISION-1 : 0] y_pipeadj_reg; // pipeline delay adjustment register
reg [OUTPUT_PRECISION-1 : 0] y_oversampler_reg;
reg [OUTPUT_PRECISION-1 : 0] luma_reg;
reg [OUTPUT_PRECISION-1 : 0] chroma_reg;
// -----------------------------------------------------------------------------
//
// COLOR BAR VALUES CCIR601 values 100/0/100/0 saturation
//
// -----------------------------------------------------------------------------
`define WHITE_Y_BAR 8'd235
`define WHITE_U_BAR 8'd128
`define WHITE_V_BAR 8'd128
`define YELLOW_Y_BAR 8'd210
`define YELLOW_U_BAR 8'd16
`define YELLOW_V_BAR 8'd146
`define CYAN_Y_BAR 8'd170
`define CYAN_U_BAR 8'd166
`define CYAN_V_BAR 8'd16
`define GREEN_Y_BAR 8'd145
`define GREEN_U_BAR 8'd54
`define GREEN_V_BAR 8'd34
`define MAGENTA_Y_BAR 8'd106
`define MAGENTA_U_BAR 8'd202
`define MAGENTA_V_BAR 8'd222
`define RED_Y_BAR 8'd81
`define RED_U_BAR 8'd90
`define RED_V_BAR 8'd240
`define BLUE_Y_BAR 8'd41
`define BLUE_U_BAR 8'd240
`define BLUE_V_BAR 8'd110
`define BLACK_Y_BAR 8'd16
`define BLACK_U_BAR 8'd128
`define BLACK_V_BAR 8'd128
`define Y_LOWBOUNDARY 8'd16
`define CRCB_LOWBOUNDARY 8'd16
`define Y_HIGHBOUNDARY 8'd235
`define CRCB_HIGHBOUNDARY 8'd240
`define Y_BLACK_LEVEL 8'd16
`define Y_WHITE_LEVEL 8'd235
// -----------------------------------------------------------------------------
//
// SCALING coefficients
//
// -----------------------------------------------------------------------------
// ----- Can be replaced by registers if needed -----
//
`define Y_SCALE_PAL 9'd82*2
`define U_SCALE_PAL 9'd141 // 70.479700 ... sinx -> 81 ..84.7
`define V_SCALE_PAL 9'd198 // 99.17593400 -> 114 ..119
`define Y_SCALE_NTSC 9'd77*2
`define U_SCALE_NTSC 9'd133 // 66.55 sinx, minimum error ->69 71
`define V_SCALE_NTSC 9'd187 // 93.65 ->97 100
`ifdef MODULATOR_CONFIGURATION_8BIT
`define SIN_45_VALUE 7'd90
`else
`define SIN_45_VALUE 8'd181
`endif
// -----------------------------------------------------------------------------
//
// SYNC LEVELS
//
// -----------------------------------------------------------------------------
`define SYNC_ADR_BLANK 3'd0
`define SYNC_ADR_LEADER 3'd1
`define SYNC_ADR_ZEROH 3'd2
`define SYNC_ADR_TRAILER 3'd3
`define SYNC_ADR_TIP 3'd4
`define SCALE_FACTOR 1
`define BLACK_SCALE 6
`define PAL_SYNC_BLANK (10'd240 << `SCALE_FACTOR)
`define PAL_SYNC_LEADER (10'd120 << `SCALE_FACTOR)
`define PAL_SYNC_ZEROH (10'd120 << `SCALE_FACTOR)
`define PAL_SYNC_TRAILER (10'd0 << `SCALE_FACTOR)
`define PAL_SYNC_TIP 10'd0
`define PAL_BLACK_LEVEL (240 << `BLACK_SCALE)
`define NTSC_SYNC_BLANK (10'd228 << `SCALE_FACTOR)
`define NTSC_SYNC_LEADER (10'd114 << `SCALE_FACTOR)
`define NTSC_SYNC_ZEROH (10'd114 << `SCALE_FACTOR)
`define NTSC_SYNC_TRAILER (10'd0 << `SCALE_FACTOR)
`define NTSC_SYNC_TIP 10'd0
`define NTSC_BLACK_LEVEL (272 << `BLACK_SCALE)
`define Y_NTSC_SCALED_BIAS (16'd13056-`NTSC_BLACK_LEVEL) //({1'b0,`Y_LOWBOUNDARY}*`Y_SCALE_NTSC)
`define Y_PAL_SCALED_BIAS (16'd14400-`PAL_BLACK_LEVEL) //({1'b0,`Y_LOWBOUNDARY}*`Y_SCALE_PAL)
// -----------------------------------------------------------------------------
//
// COLOR BURST LEVELS
//
// -----------------------------------------------------------------------------
// PAL burst phase is Uphase +135/-225 degrees
`define U_BURST_PAL (-22)
`define V_BURST_PAL ( 22)
// NTSC burst phase is U phase -180 degrees
`define U_BURST_NTSC (-30)
`define V_BURST_NTSC ( 0)
// -----------------------------------------------------------------------------
//
// COLOR BARS MULTIPLEXER
//
// -----------------------------------------------------------------------------
always @(color_bars)
case (color_bars)
(3'd0) : begin
y_bars = `WHITE_Y_BAR;
u_bars = `WHITE_U_BAR;
v_bars = `WHITE_V_BAR;
end
(3'd1) : begin
y_bars = `YELLOW_Y_BAR;
u_bars = `YELLOW_U_BAR;
v_bars = `YELLOW_V_BAR;
end
(3'd2) : begin
y_bars = `CYAN_Y_BAR;
u_bars = `CYAN_U_BAR;
v_bars = `CYAN_V_BAR;
end
(3'd3) : begin
y_bars = `GREEN_Y_BAR;
u_bars = `GREEN_U_BAR;
v_bars = `GREEN_V_BAR;
end
(3'd4) : begin
y_bars = `MAGENTA_Y_BAR;
u_bars = `MAGENTA_U_BAR;
v_bars = `MAGENTA_V_BAR;
end
(3'd5) : begin
y_bars = `RED_Y_BAR;
u_bars = `RED_U_BAR;
v_bars = `RED_V_BAR;
end
(3'd6) : begin
y_bars = `BLUE_Y_BAR;
u_bars = `BLUE_U_BAR;
v_bars = `BLUE_V_BAR;
end
default: begin
y_bars = `BLACK_Y_BAR;
u_bars = `BLACK_U_BAR;
v_bars = `BLACK_V_BAR;
end
endcase
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