📄 dve_ccir_top.v
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// -----------------------------------------------------------------------------
//
//
// D I G I T A L C O L O R V I D E O E N C O D E R
//
// 27 MHZ CCIR601/ITU-R BT-470.3 COMPLIANT
//
// DIGITAL COLOR VIDEO ENCODER
// Project TOP ENTITY
// Version : 2.0
//
// Copyright (c) 1998 Maxim Vlassov (maxismsx@hotmail.com)
//
//
// All rights reserved
//
// Redistribution and reuse of source code and synthesized forms of this source code and it's
// derivatives is strictly permitted under the following conditions:
//
// Redistributions of source code MUST retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions of code in synthesized form MUST reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
//
// Any derivated work from the current design could be not synchronized with the
// latest design updates. Report any design reuse issues to the author.
// Lates release notes and design relseases are available upon request via e-mail.
//
// -----------------------------------------------------------------------------
//
// Revision history:
// Version 1.0 from 10/02/1998 - Initical version
// Verison 1.1 from 01/04/1998 - Production version (minor changes, parametrization added)
// Version 1.2 - 1.9 - slight code optimization for FPGA implementation
// Version 2.0 from 01/01/2002 - NTSC mode / progressive/interlace scan modes implemented
//
//
// -----------------------------------------------------------------------------
// Implementation details:
// clock : Single clock domain, 27.000 MHz clock source, 50% duty cycle
// sequential logic: D-FF based, positive clock edge driven
// scan chaines, scan controller: absent
// reset : synchronous, active low
//
module dve_ccir_top (sclk,
rst_n,
apb_pstb,
apb_sel,
apb_pwrite,
apb_write,
apb_read,
pixel_in,
hsync_out,
vsync_out,
csync_out,
luma_out,
chroma_out,
fcbs_out
);
`undef DEBUG_MODE
// -----------------------------------------------------------------------------
//
// USER DEFINED SECTION
//
// -----------------------------------------------------------------------------
parameter INPUT_PRECISION = 8;
parameter OUTPUT_PRECISION = 10;
parameter SUBCARRIER_INTEGER_PRECISION = 11;
// -----------------------------------------------------------------------------
//
// END OF USER DEFINED SECTION
//
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
//
// Parameter propagation section
//
// CONFIGURES all the modules thoughout the design
//
// -----------------------------------------------------------------------------
defparam
dve_ccir_top.DATAPATH.INPUT_PRECISION = INPUT_PRECISION,
dve_ccir_top.DATAPATH.OUTPUT_PRECISION = OUTPUT_PRECISION,
dve_ccir_top.DATAPATH.SUBCARRIER_INTEGER_PRECISION = SUBCARRIER_INTEGER_PRECISION,
dve_ccir_top.SYNTHESIZER.SUBCARRIER_INTEGER_PRECISION = SUBCARRIER_INTEGER_PRECISION;
parameter SYNC_LEVELS_NUMBER=3;
//Uncomment the line below for test purposes
//`define DEBUG_MODE_SYN
// -----------------------------------------------------------------------------
//
// I/Os and other resource declaration
//
// -----------------------------------------------------------------------------
input sclk; // synchronous pixel clock input (4Fsc)
// 27.000000 MHz clock
//
input rst_n; // synchronous reset input
input apb_pstb; // APB port strobe input
input apb_sel; // APB module selection input
input apb_pwrite; // APB port write command
input [7 : 0] apb_write; // APB write data bus
output [7 : 0] apb_read; // APB read data bus
// chip-wide reset (generated by reset controller)
input [INPUT_PRECISION-1 : 0] pixel_in; // Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 multiplex
output hsync_out;
output vsync_out;
output csync_out;
output [OUTPUT_PRECISION-1 : 0] luma_out;
output [OUTPUT_PRECISION-1 : 0] chroma_out;
output [OUTPUT_PRECISION-1 : 0] fcbs_out;
wire srst_n; // synchronous, active low,
wire y_gate, cb_gate, cr_gate;
wire coding_ntsc,burst_gate,pal_v_flag;
wire color_bars_mode;
wire [2 : 0] color_bars;
wire [SUBCARRIER_INTEGER_PRECISION-1 : 0] fsc_tbl_addr; // Integer phase, look-up table direct address
wire set_phase_flag; // flag, which clears the phase
wire [1 : 0] frame_number; // 0/90/180/270
wire [SYNC_LEVELS_NUMBER-1 : 0] sync_levels;
wire end_of_line_flag;
wire video_enable;
wire [SUBCARRIER_INTEGER_PRECISION-1 : 0] fsc_tbl_addr_gen;
// -----------------------------------------------------------------------------
//
//..... Subcarrier debug feature .....
//
// -----------------------------------------------------------------------------
`ifdef DEBUG_MODE_SYN
reg [SUBCARRIER_INTEGER_PRECISION-1 : 0] fsc_test_counter;
//..... Subcarrier synthesized test counter .....
always @(posedge sclk)
if (~srst_n) fsc_test_counter <= 0;
else fsc_test_counter <= fsc_test_counter + 1;
assign fsc_tbl_addr = fsc_test_counter;
`else
assign fsc_tbl_addr = fsc_tbl_addr_gen;
`endif
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
//
// DIGITAL VIDEO DATAPATH MODULE
//
// -----------------------------------------------------------------------------
dve_ccir_dph DATAPATH (.sclk(sclk),
.srst_n(srst_n),
.pixel_in(pixel_in),
.y_gate(y_gate),
.cb_gate(cb_gate),
.cr_gate(cr_gate),
.coding_ntsc(coding_ntsc),
.sync_levels(sync_levels),
.burst_gate(burst_gate),
.video_enable(video_enable),
.pal_v_flag(pal_v_flag),
.color_bars_mode(color_bars_mode),
.color_bars(color_bars),
.fsc_tbl_addr(fsc_tbl_addr),
.luma_out(luma_out),
.chroma_out(chroma_out),
.fcbs_out(fcbs_out));
// -----------------------------------------------------------------------------
//
// DIRECT DIGITAL SYNTHESIS MODULE
//
// -----------------------------------------------------------------------------
dve_ccir_dds SYNTHESIZER(.sclk(sclk),
.srst_n(srst_n),
.coding_ntsc(coding_ntsc),
.set_phase_flag(set_phase_flag),
.frame_number(frame_number),
.end_of_line_flag(end_of_line_flag),
.fsc_tbl_addr(fsc_tbl_addr_gen));
// -----------------------------------------------------------------------------
//
// RECONFIGURABLE VIDEO TIMING GENERATOR
//
// -----------------------------------------------------------------------------
dve_ccir_vtg GENERATOR(.sclk(sclk),
.srst_n(srst_n),
.coding_ntsc(coding_ntsc),
.burst_gate(burst_gate),
.video_enable(video_enable),
.pal_v_flag(pal_v_flag),
.color_bars(color_bars),
.y_gate(y_gate),
.cr_gate(cr_gate),
.cb_gate(cb_gate),
.csync_out(csync_out),
.vsync_out(vsync_out),
.hsync_out(hsync_out),
.set_phase_flag(set_phase_flag),
.frame_number(frame_number),
.end_of_line_flag(end_of_line_flag),
.sync_levels(sync_levels)
);
// -----------------------------------------------------------------------------
//
// HOST ARM APB SLAVE PORT
//
// -----------------------------------------------------------------------------
dve_ccir_aps INTERFACE
(.sclk(sclk),
.rst_n(rst_n),
.apb_pstb(apb_pstb),
.apb_sel(apb_sel),
.apb_pwrite(apb_pwrite),
.apb_write(apb_write),
.apb_read(apb_read),
.coding_ntsc(coding_ntsc),
.srst_n(srst_n),
.color_bars_mode(color_bars_mode)
);
endmodule // dve_ccir_top
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