dve_ccir_mlt8x9.v

全电视信号编码器

// -----------------------------------------------------------------------------
//
//
//                  D I G I T A L   C O L O R   V I D E O   E N C O D E R
//       
//                  27 MHZ CCIR601/ITU-R BT-470.3 COMPLIANT
//
// PARALLEL HIGH SPEED BOOTH MULTIPLIER WITH WALLACE-TREE COMPRESSION SUMMATOR
// Asymmetrical multiplication 8 bits by 9 bits : 16 bits product
// Version : 2.0
//
// Copyright (c) 1998 Maxim Vlassov ([e-mail])
// 
//
// All rights reserved
//
// Redistribution and reuse of source code and synthesized forms of this source code and it's
// derivatives is strictly permitted under the following conditions:
//
// Redistributions of source code MUST retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions of code in synthesized form MUST reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
//
// Any derivated work from the current design could be not synchronized with the
// latest design updates. Report any design reuse issues to the author.
// Lates release notes and design releases are available upon request via e-mail.
//
// -----------------------------------------------------------------------------
// USER NOTES: UNCOMMENT THE "pipelined" definition to enable the pipelined 
// operation
// -----------------------------------------------------------------------------
//
//
// Revision history:
// Version 1.0 from 10/02/1998 - Initical version 
// Verison 1.1 from 01/04/1998 - Production version (minor changes, parametrization added)
// Version 1.2 - 1.9 - slight code optimization for FPGA implementation
// Version 2.0 from 01/01/2002 - NTSC mode / progressive/interlace scan modes implemented
//
//
// -----------------------------------------------------------------------------
//
// Operation principle: Partial products are fed to the optimized Wallace tree
//
// -----------------------------------------------------------------------------
module dve_ccir_mlt8x9 (sclk,
              srst_n,
              a_in,
              b_in,
              p_out);

			  
input sclk;
input srst_n;

parameter A_WIDTH=8;
parameter B_WIDTH=9;

input [A_WIDTH-1 : 0] a_in;
input [B_WIDTH-1 : 0] b_in;
output[A_WIDTH+B_WIDTH-2 : 0] p_out;

`undef pipelined

// -----------------------------------------------------------------------------
//
//                      USER SECTION
//
// -----------------------------------------------------------------------------

// -----------------------------------------------------------------------------
// Uncomment define directive to enable pipelining
// -----------------------------------------------------------------------------

//`define pipelined

// -----------------------------------------------------------------------------
//                       END OF USER SECTION
// -----------------------------------------------------------------------------

wire p_c_0_0,p_c_1_0,p_o_2_0,p_c_2_0,p_c_2_1,p_o_3_0,p_c_3_0,p_c_3_1,p_o_4_0,p_o_4_1,p_c_4_0,p_c_4_1,p_c_4_2,
     p_o_5_0,p_o_5_1,p_c_5_0,p_c_5_1,p_c_5_2,p_o_6_0,p_o_6_1,p_o_6_2,p_c_6_0,p_c_6_1,p_c_6_2,p_c_6_3,
     p_o_7_0,p_o_7_1,p_o_7_2,p_c_7_0,p_c_7_1,p_c_7_2,p_c_7_3,p_o_8_0,p_o_8_1,p_o_8_2,p_c_8_0,p_c_8_1,
     p_c_8_2,p_c_8_3,p_o_9_0,p_o_9_1,p_o_9_2,p_c_9_0,p_c_9_1,p_c_9_2,p_c_9_3,p_o_10_0,p_o_10_1,p_o_10_2,
     p_c_10_0,p_c_10_1,p_c_10_2,p_c_10_3,p_o_11_0,p_o_11_1,p_o_11_2,p_c_11_0,p_c_11_1,p_c_11_2,p_c_11_3,
     p_o_12_0,p_o_12_1,p_c_12_0,p_c_12_1,p_c_12_2,p_o_13_0,p_c_13_0,p_c_13_1,p_o_14_0,p_c_14_0,p_c_14_1;

`ifdef pipelined	 
reg [B_WIDTH : 0] p_a, p_b, p_c, p_d; 
reg s_a,s_b,s_c,s_d;
`else
wire [B_WIDTH : 0] p_a, p_b, p_c,p_d; 
wire s_a,s_b,s_c,s_d;
`endif
	 
//---------------------------------------------------------------------------------------
//
// Partial products computation.
// Either first stage of a pipeline, or a combinational logic part
//
//---------------------------------------------------------------------------------------
`ifdef pipelined
always @(posedge sclk)
begin
 if (!srst_n)
  begin
   p_a <= 9'b0;		 
   p_b <= 9'b0;		 
   p_c <= 9'b0;		 
   p_d <= 9'b0;		 
   s_a <= 1'b0;
   s_b <= 1'b0;
   s_c <= 1'b0;
   s_d <= 1'b0;
  end
 else
  begin
   p_a <= booth_compressor ({a_in[1:0],1'b0},b_in);
   p_b <= booth_compressor (a_in[3:1],b_in);
   p_c <= booth_compressor (a_in[5:3],b_in);
   p_d <= booth_compressor (a_in[7:5],b_in);
   s_a <= compliment_sign({a_in[1:0],1'b0});
   s_b <= compliment_sign(a_in[3:1]);
   s_c <= compliment_sign(a_in[5:3]);
   s_d <= compliment_sign(a_in[7:5]);
  end
end

`else
assign  p_a = booth_compressor ({a_in[1:0],1'b0},b_in);
assign  p_b = booth_compressor (a_in[3:1],b_in);
assign  p_c = booth_compressor (a_in[5:3],b_in);
assign  p_d = booth_compressor (a_in[7:5],b_in);
assign  s_a = compliment_sign({a_in[1:0],1'b0});
assign  s_b = compliment_sign(a_in[3:1]);
assign  s_c = compliment_sign(a_in[5:3]);
assign  s_d = compliment_sign(a_in[7:5]);
`endif


//assign p_out = {4'b0,~p_a[9],p_a[9],p_a[9],p_a[8 : 0]}+
//        {4'b0, ~p_b[9], p_b[8 : 0], 2'b0} +
//        {2'b0, ~p_c[9], p_c[8 : 0], 4'b0} +
//        {~p_d[9], p_d[8 : 0], 6'b0} +
//        {9'b010100000,s_d,1'b0,s_c,1'b0,s_b,1'b0,s_a};
   
// -----------------------------------------------------------------------------
//
// Wallace-tree adder with "prevention of sign extension" algorithm option
//
// -----------------------------------------------------------------------------
assign p_out[0] = ha(p_a[0],s_a);
assign p_c_0_0  = hc(p_a[0],s_a);

assign p_out[1] = ha(p_a[1],p_c_0_0);
assign p_c_1_0  = hc(p_a[1],p_c_0_0);
 
assign p_o_2_0  = fa(p_a[2],p_b[0],s_b);
assign p_out[2] = ha(p_o_2_0,p_c_1_0);
assign p_c_2_0  = fc(p_a[2],p_b[0],s_b);
assign p_c_2_1  = hc(p_o_2_0,p_c_1_0);

assign p_o_3_0  = ha(p_a[3],p_b[1]);
assign p_out[3] = fa(p_c_2_0,p_c_2_1,p_o_3_0);
assign p_c_3_0  = hc(p_a[3],p_b[1]);
assign p_c_3_1  = fc(p_c_2_0,p_c_2_1,p_o_3_0);

assign p_o_4_0  = fa(p_a[4],p_b[2],p_c[0]);
assign p_o_4_1  = ha(p_c_3_0,s_c);
assign p_out[4] = fa(p_o_4_0,p_o_4_1,p_c_3_1);
assign p_c_4_0  = fc(p_a[4],p_b[2],p_c[0]);
assign p_c_4_1  = hc(p_c_3_0,s_c);
assign p_c_4_2  = fc(p_o_4_0,p_o_4_1,p_c_3_1);

assign p_o_5_0  = fa(p_a[5],p_b[3],p_c[1]);
assign p_o_5_1  = ha(p_o_5_0,p_c_4_0);
assign p_out[5] = fa(p_o_5_1,p_c_4_1,p_c_4_2);
assign p_c_5_0  = fc(p_a[5],p_b[3],p_c[1]);
assign p_c_5_1  = hc(p_o_5_0,p_c_4_0);
assign p_c_5_2  = fc(p_o_5_1,p_c_4_1,p_c_4_2);

assign p_o_6_0  = fa(p_a[6],p_b[4],p_c[2]);
assign p_o_6_1  = ha(p_d[0],s_d);
assign p_o_6_2  = fa(p_o_6_0,p_o_6_1,p_c_5_0);
assign p_out[6] = fa(p_o_6_2,p_c_5_1,p_c_5_2);
assign p_c_6_0  = fc(p_a[6],p_b[4],p_c[2]);
assign p_c_6_1  = hc(p_d[0],s_d);
assign p_c_6_2  = fc(p_o_6_0,p_o_6_1,p_c_5_0);
assign p_c_6_3  = fc(p_o_6_2,p_c_5_1,p_c_5_2);

assign p_o_7_0  = fa(p_a[7],p_b[5],p_c[3]);
assign p_o_7_1  = ha(p_d[1],p_c_6_0);
assign p_o_7_2  = fa(p_o_7_0,p_o_7_1,p_c_6_1);
assign p_out[7] = fa(p_o_7_2,p_c_6_2,p_c_6_3);
assign p_c_7_0  = fc(p_a[7],p_b[5],p_c[3]);
assign p_c_7_1  = hc(p_d[1],p_c_6_0);
assign p_c_7_2  = fc(p_o_7_0,p_o_7_1,p_c_6_1);
assign p_c_7_3  = fc(p_o_7_2,p_c_6_2,p_c_6_3);

assign p_o_8_0  = fa(p_a[8],p_b[6],p_c[4]);
assign p_o_8_1  = ha(p_d[2],p_c_7_0);
assign p_o_8_2  = fa(p_o_8_0,p_o_8_1,p_c_7_1);
assign p_out[8] = fa(p_o_8_2,p_c_7_2,p_c_7_3);
assign p_c_8_0  = fc(p_a[8],p_b[6],p_c[4]);
assign p_c_8_1  = hc(p_d[2],p_c_7_0);
assign p_c_8_2  = fc(p_o_8_0,p_o_8_1,p_c_7_1);
assign p_c_8_3  = fc(p_o_8_2,p_c_7_2,p_c_7_3);

// p_a[9],p_b[7],p_c[5],p_d[3],p_c_8_0,p_c_8_1,p_c_8_2,p_c_8_3
assign p_o_9_0  = fa(p_a[9],p_b[7],p_c[5]);
assign p_o_9_1  = ha(p_d[3],p_c_8_0);
assign p_o_9_2  = fa(p_o_9_0,p_o_9_1,p_c_8_1);
assign p_out[9] = fa(p_o_9_2,p_c_8_2,p_c_8_3);
assign p_c_9_0  = fc(p_a[9],p_b[7],p_c[5]);
assign p_c_9_1  = hc(p_d[3],p_c_8_0);
assign p_c_9_2  = fc(p_o_9_0,p_o_9_1,p_c_8_1);
assign p_c_9_3  = fc(p_o_9_2,p_c_8_2,p_c_8_3);

// p_a[9],p_b[8],p_c[6],p_d[4],p_c_9_0,p_c_9_1,p_c_9_2,p_c_9_3
assign p_o_10_0 = fa(p_a[9],p_b[8],p_c[6]);
assign p_o_10_1 = ha(p_d[4],p_c_9_0);
assign p_o_10_2 = fa(p_o_10_0,p_o_10_1,p_c_9_1);
assign p_out[10]= fa(p_o_10_2,p_c_9_2,p_c_9_3);
assign p_c_10_0 = fc(p_a[9],p_b[8],p_c[6]);
assign p_c_10_1 = hc(p_d[4],p_c_9_0);
assign p_c_10_2 = fc(p_o_10_0,p_o_10_1,p_c_9_1);
assign p_c_10_3 = fc(p_o_10_2,p_c_9_2,p_c_9_3);
 
// p_a[9],p_b[9],p_c[7],p_d[5],p_c_10_0,p_c_10_1,p_c_10_2,p_c_10_3
assign p_o_11_0 = fa(p_a[9],p_b[9],p_c[7]);
assign p_o_11_1 = ha(p_d[5],p_c_10_0);
assign p_o_11_2 = fa(p_o_11_0,p_o_11_1,p_c_10_1);
assign p_out[11]= fa(p_o_11_2,p_c_10_2,p_c_10_3);
assign p_c_11_0 = ic(p_a[9],p_b[9],p_c[7]);
assign p_c_11_1 = hc(p_d[5],p_c_10_0);
assign p_c_11_2 = fc(p_o_11_0,p_o_11_1,p_c_10_1);
assign p_c_11_3 = fc(p_o_11_2,p_c_10_2,p_c_10_3);
 
// 1'b1, p_c[8],p_d[6],p_c_11_0,p_c_11_1,p_c_11_2,p_c_11_3
assign p_o_12_0 = fa(1'b1,p_c[8],p_d[6]);
assign p_o_12_1 = fa(p_o_12_0,p_c_11_0,p_c_11_1);
assign p_out[12]= fa(p_o_12_1,p_c_11_2,p_c_11_3);
assign p_c_12_0 = fc(1'b1,p_c[8],p_d[6]);
assign p_c_12_1 = fc(p_o_12_0,p_c_11_0,p_c_11_1);
assign p_c_12_2 = fc(p_o_12_1,p_c_11_2,p_c_11_3);

// p_c[9],p_d[7],p_c_12_0,p_c_12_1,p_c_12_2
assign p_o_13_0  = ma(p_c[9],p_d[7],p_c_12_0);
assign p_out[13] = fa(p_o_13_0,p_c_12_1,p_c_12_2);
assign p_c_13_0  = mc(p_c[9],p_d[7],p_c_12_0);
assign p_c_13_1  = fc(p_o_13_0,p_c_12_1,p_c_12_2);

// 1'b1, p_d[8],p_c_13_0,p_c_13_1
assign p_o_14_0 = ha(1'b1,p_d[8]);
assign p_out[14]= fa(p_o_14_0,p_c_13_0,p_c_13_1);
assign p_c_14_0 = hc(1'b1,p_d[8]);
assign p_c_14_1 = fc(p_o_14_0,p_c_13_0,p_c_13_1);

// p_d[9],p_c_14_0,p_c_14_1
assign p_out[15]= ma(p_d[9],p_c_14_0,p_c_14_1);

// -----------------------------------------------------------------------------
//
// Booth compressor-barrel shifter. Depending on the input value it performs
// shift/invert operation or clears the output result
//
// -----------------------------------------------------------------------------
function [B_WIDTH : 0] booth_compressor;
input [2 : 0] triade;
input [B_WIDTH-1 : 0] argument;
begin
 case (triade)
// Bypass the operand *1
  3'b001,3'b010 :  booth_compressor={argument[B_WIDTH-1],argument};
// Double the operand *2
  3'b011 : booth_compressor = {argument, 1'b0};
// Compliment the operand
  3'b101, 3'b110 :  booth_compressor=~{argument[B_WIDTH-1],argument};
// Shift and Compliment the operand 
  3'b100 : booth_compressor = {~argument, 1'b1}; // Zero the operand  x0
  3'b000, 3'b111 : booth_compressor = {B_WIDTH{1'b0}};
  default:  booth_compressor = {B_WIDTH{1'b0}};
 endcase
end 
endfunction

// -----------------------------------------------------------------------------
//
// Function, which checks the conditions under which the result is complimented
//
// -----------------------------------------------------------------------------
function compliment_sign;
input [2:0] triade;
begin
 case (triade)
  3'b101, 3'b110, 3'b100 : compliment_sign = 1'b1;
  default : compliment_sign = 1'b0;
 endcase
end
endfunction

// -----------------------------------------------------------------------------
//
// Set of basic arithmetic functions
//
// -----------------------------------------------------------------------------
// Full adder function
function fa;
 input a;
 input b;
 input c;
 begin
  fa=a^b^c;
 end
endfunction
// Half adder function
function ha;
 input a;
 input b;
 begin
  ha=a^b;
 end
endfunction
// Full carry generator
function fc;
 input a;
 input b;
 input c;
 begin
  fc=a&b | a&c | b&c;
 end
endfunction
// Half carry generator
function hc;
 input a;
 input b;
 begin
  hc=a&b;
 end
endfunction
// Full carry generator with two inverted inputs
function ic;
 input a;
 input b;
 input c;
 begin
  ic=(~a & ~b) | (~a  | ~b)&c;
 end
endfunction
// Full adder function with one inverted input
function ma;
 input a;
 input b;
 input c;
 begin
  ma=~a^b^c;
 end
endfunction
// Full carry generator with one inverted input
function mc;
 input a;
 input b;
 input c;
 begin
  mc=~a&b | ~a&c | b&c;
 end
endfunction

endmodule //dve_ccir_mlt