📄 dve_ccir_vtg.v
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// -----------------------------------------------------------------------------
//
//
// D I G I T A L C O L O R V I D E O E N C O D E R
//
// 27 MHZ CCIR601/ITU-R BT-470.3 COMPLIANT
//
// Digital Video Encoder (DVE) CCCIR601/RS-170A compliant Video Timing Generator (VTG) module
// Version : 2.0
//
// Copyright (c) 1998 Maxim Vlassov (maxismsx@hotmail.com)
//
//
// All rights reserved
//
// Redistribution and reuse of source code and synthesized forms of this source code and it's
// derivatives is strictly permitted under the following conditions:
//
// Redistributions of source code MUST retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions of code in synthesized form MUST reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
//
// Any derivated work from the current design could be not synchronized with the
// latest design updates. Report any design reuse issues to the author.
// Lates release notes and design relseases are available upon request via e-mail.
//
// -----------------------------------------------------------------------------
//
// Revision history:
// Version 1.0 from 10/02/1998 - Initical version
// Verison 1.1 from 10/04/1998 - Production version (minor changes, parametrization added)
// Version 1.2 - 1.9 - slight code optimization for FPGA implementation
// Version 2.0 from 01/01/2002 - NTSC mode / progressive/interlace scan modes implemented
//
//
// -----------------------------------------------------------------------------
module dve_ccir_vtg
(sclk,
srst_n,
coding_ntsc,
burst_gate,
video_enable,
pal_v_flag,
color_bars,
y_gate,
cb_gate,
cr_gate,
csync_out,
hsync_out,
vsync_out,
set_phase_flag,
end_of_line_flag,
frame_number,
sync_levels
);
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// -----------------------------------------------------------------------------
// USER-defined parameters
// -----------------------------------------------------------------------------
parameter PIXEL_COUNTER_WIDTH=10;
parameter HALFLINE_COUNTER_WIDTH=10;
parameter LINE_COUNTER_WIDTH = HALFLINE_COUNTER_WIDTH;
parameter SYNC_LEVELS_NUMBER=3;
// -----------------------------------------------------------------------------
// PORTS and INTERNAL RESOURCES declarations
// -----------------------------------------------------------------------------
input sclk; // synchronous pixel clock input 27.000 MHz
input srst_n; // synchronous, active low,
// chip-wide reset (generated by reset controller)
input coding_ntsc; // =1 NTSC mode
output burst_gate; // Dynamically inserts the burst value
output pal_v_flag; // when 1, V+, otherwise V-
output video_enable; // When 1, the video data is enabled
output [2 : 0] color_bars; // The current number of the color bar
output y_gate; // Enables the Y data pipe
output cb_gate; // Enables the U data pipe
output cr_gate; // Enables the V data pipe
output csync_out; // Composite sync output (negative)
output vsync_out; // Vertical output (negative)
output hsync_out; // Horizontal output (negative)
output set_phase_flag; // When 1, the DDS will be loaded with new phase
output [1 : 0] frame_number; // 0/90/180 or 270 degrees as the initial phase
output [SYNC_LEVELS_NUMBER-1 : 0] sync_levels;
output end_of_line_flag; // Active, when end of line is reached
reg [PIXEL_COUNTER_WIDTH-1 : 0] pixel_counter;
reg [PIXEL_COUNTER_WIDTH : 0] timeline_counter; // Counts along the scan line
reg [HALFLINE_COUNTER_WIDTH-1 : 0] halfline_counter;
reg [HALFLINE_COUNTER_WIDTH-1 : 0] last_halfline_reg; // Stores the current halfline number
reg [LINE_COUNTER_WIDTH - 1 : 0] line_counter; // Counts lines through the whole frame
// -----------------------------------------------------------------------------
// Line timing state machine registers. ONE HOT implementation :
// -----------------------------------------------------------------------------
reg sm_sc_preequ_reg; // Preequalization state
reg sm_sc_serr_reg; // Serration
reg sm_sc_postequ_reg; // Postequalizatoin state
reg sm_sc_linespace_reg; // Active line space register
// -----------------------------------------------------------------------------
// Frame ODD/EVEN state machine ONE HOT implementation :
// -----------------------------------------------------------------------------
reg sm_first_frame_reg;
reg sm_fields_one_to_four_reg;
wire last_halfline; // The output of the halfline comparator
wire last_line_sample; // Flag, which signals the end of line
wire last_line; // Comparator output for the line counter
reg sm_first_halfline_reg; // State machine, which controls the number of
// samples per line
// -----------------------------------------------------------------------------
// Color burst SM control flags
// -----------------------------------------------------------------------------
wire color_burst_on; // Flag to enable scan-line color
wire color_burst_off; // Flag to disable scan-line color
wire burst_gate_on; // Flag to enable color burst
wire burst_gate_off; // Flag to disable color burst
wire line_video_on; // Enable the video for the line
wire line_video_off; // Disable the video
wire active_video_on;
wire active_video_off;
// -----------------------------------------------------------------------------
// Color burst and bloanking SMs
// -----------------------------------------------------------------------------
reg sm_burst_enable_reg; // Enable colorburst on the line
reg sm_burst_gate_reg; // Insert colorburst immediatly
reg sm_activeline_reg; // Enables the video per line
reg sm_videoenable_reg; // Dynamically blanks the video
// -----------------------------------------------------------------------------
// The "end of sync tip" comparators
// -----------------------------------------------------------------------------
wire end_of_sync_line; // End of sync on the line
wire end_of_sync_serr; // End of sync on serration
wire end_of_sync_equ; // End of sync on equilization
// -----------------------------------------------------------------------------
// Synchro SM control flags
// -----------------------------------------------------------------------------
wire start_sync; // Start sync tip
wire end_sync; // End sync tip
// -----------------------------------------------------------------------------
// Line number comparators for the PAL compensation
// -----------------------------------------------------------------------------
wire middle_of_frame; //
wire end_of_frame;
// -----------------------------------------------------------------------------
// The synchro-tip state machine
// -----------------------------------------------------------------------------
parameter TIP_SM_WIDTH = 3;
`define SYNC_TIP_IDLE 3'd0
`define SYNC_TIP_LEADER 3'd1
`define SYNC_TIP_ZEROH 3'd2
`define SYNC_TIP_TRAILER 3'd3
`define SYNC_TIP_LEVEL 3'd4
`define BLACK_LUMA_CODE 3'd7
`define SYNC_STAT_ACTIVE 1'b1
`define SYNC_STAT_PASSIVE 1'b0
reg [TIP_SM_WIDTH-1 : 0] sm_tip_state;
reg [TIP_SM_WIDTH-1 : 0] sm_tip_next;
reg sm_tipstat;
reg sm_tipstat_next;
// -----------------------------------------------------------------------------
// Take the positive value of V or negative. When =0 => +V, ColorBurst=135 Grad
// When 1 => -V, ColorBurst=225 Grad
// -----------------------------------------------------------------------------
wire positive_v_flag;
// -----------------------------------------------------------------------------
// Color bars machine
// -----------------------------------------------------------------------------
wire next_color_bar;
reg [2 : 0] color_bars_counter; // color bars counter
reg [8 : 0] bar_width_counter; // color bars length
// -----------------------------------------------------------------------------
// Y/U/V clock gating state machine
// -----------------------------------------------------------------------------
reg y_gate_reg; // Y gate state machine
reg y_even_sample_reg; // =1 Even sample =0 Odd sample
reg cr_gate_reg; //
reg cb_gate_reg; //
// -----------------------------------------------------------------------------
// Sync state machines
// -----------------------------------------------------------------------------
reg csync_out; // Composite synchronization
reg vsync_out; // Vertical synchronization
reg sm_hsync_reg; // Horizontal synchronization
// -----------------------------------------------------------------------------
// TIMING READJUSTMENT REGISTERS
// -----------------------------------------------------------------------------
reg set_phase_flag_del_0_reg, set_phase_flag_del_1_reg, set_phase_flag_del_2_reg,
set_phase_flag_del_3_reg;
reg [1 : 0] frame_num_del_0_reg, frame_num_del_1_reg, frame_num_del_2_reg, frame_num_del_3_reg;
reg end_of_flag_del_0_reg, end_of_flag_del_1_reg, end_of_flag_del_2_reg,
end_of_flag_del_3_reg;
`define PAL_SYNPULSE_NUMBER (10'd5 - 10'd1) // In PAL mode there are 5 pre/post equ, 5 serr. pulses
`define NTSC_SYNPULSE_NUMBER (10'd6 - 10'd1) // In NTSC mode there are 6 pre/post equ, 6 serr. pulses
`define PAL_HALFLINE_NUMBER (10'd610-10'd1) // 610 halflines per active space
`define NTSC_HALFLINE_NUMBER (10'd507-10'd1) // 507 halflines per active space
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