datareg.v

计算器芯片的verilog实现代码！ 时序仿真成功

module DATAREG(output reg [31:0] read_date ,
			 input [4:0] write_addr, read_addr,
				input [31:0] read_data);

	reg [31:0] data_reg [31:0];

	always
		begin
		end
		
endmodule