recordsecond_reg.v

实用闹钟的verilog代码。不是vhdl的！经过ldv验证

moudle RECORDSECOND_REG (output reg [27:0] record_out,
													input [27:0] record_in ,
													input forward , back , 
													bus_in_control ,bus_out_control );





endmoudle




module DATA_BUS (output [27:0] record_bus_out,
									input [27:0] record_bus_in ,
									input record_bus_in , record_bus_out);




endmoudle





moudle 32_REG (output reg [7:0] record_out,
								input [27:0] record_in ,
								input forward , back );




endmoudle