recordsecond_reg.v.bak

实用闹钟的verilog代码。不是vhdl的！经过ldv验证

moudle RECORDSECOND_REG (output reg [6:0] record_out,
				input [6:0] record_in ,
				input forward , back , 
							bus_in_control ,bus_out_control );




endmoudle