mux8.vhd

来自「福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd）」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
entity mux8 is
	port(data0:in std_logic_vector(3 downto 0);
		 data1:in std_logic_vector(3 downto 0);
		 data2:in std_logic_vector(3 downto 0);
		 data3:in std_logic_vector(3 downto 0);
		 data4:in std_logic_vector(3 downto 0);
		 data5:in std_logic_vector(3 downto 0);
		 data6:in std_logic_vector(3 downto 0);
		 data7:in std_logic_vector(3 downto 0);
		 sel:  in std_logic_vector(2 downto 0);
		 result: out std_logic_vector(3 downto 0));
end mux8;
architecture behavemux8 of mux8 is
begin
	process(sel)
	begin
		case sel is
			when "000" => result <= data0;
			when "001" => result <= data1;
			when "010" => result <= data2;
			when "011" => result <= data3;
			when "100" => result <= data4;
			when "101" => result <= data5;
			when "110" => result <= data6;
			when "111" => result <= data7;
			when others => result <= "0000";
		end case;
	end process;
end behavemux8;