addr.vhd

来自「福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd）」· VHDL 代码 · 共 17 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY addr IS
	PORT(a,b,cin:IN std_logic;
	s,co:OUT std_logic);
END addr;
ARCHITECTURE full OF addr IS
COMPONENT halfaddr
	PORT(a,b:IN STD_LOGIC;s,co:OUT STD_LOGIC);
END COMPONENT;
SIGNAL u_c,u_s,u1_c:std_logic;
begin
u0:halfaddr PORT MAP(a,b,u_s,u_c);
u1:halfaddr PORT MAP(u_s,cin,s,u1_c);
co<= u_c or u1_c;
end full;