control.vhd

福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd）

library ieee;
use ieee.std_logic_1164.all;
entity control is
	port(clkin:	in	std_logic;
		 ena_cnt:	out	std_logic;
		 clr_cnt:	out	std_logic;
		 load:	out	std_logic);
end entity;
architecture behv of control is
	signal	ena,clr,loadtemp:std_logic;
begin
	process(clkin,ena)
	begin
		if clkin'event and clkin='1' then
			ena<=not ena;
			
		end if;
		clr<=not clkin and not ena;
	end process;
		
	clr_cnt<=clr;
	ena_cnt<=ena;
	load<=not ena;
end behv;