myreg.vhd

来自「福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd）」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
entity myreg is
	port(data0:in std_logic_vector(3 downto 0);
		 data1:in std_logic_vector(3 downto 0);
		 data2:in std_logic_vector(3 downto 0);
		 data3:in std_logic_vector(3 downto 0);
		 data4:in std_logic_vector(3 downto 0);
		 data5:in std_logic_vector(3 downto 0);
		 data6:in std_logic_vector(3 downto 0);
		 data7:in std_logic_vector(3 downto 0);
		 load: in std_logic;
		 dout0:out std_logic_vector(3 downto 0);
		 dout1:out std_logic_vector(3 downto 0);
		 dout2:out std_logic_vector(3 downto 0);
		 dout3:out std_logic_vector(3 downto 0);
		 dout4:out std_logic_vector(3 downto 0);
		 dout5:out std_logic_vector(3 downto 0);
		 dout6:out std_logic_vector(3 downto 0);
		 dout7:out std_logic_vector(3 downto 0));
end myreg;
architecture behv of myreg is
	signal d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(3 downto 0);
begin
	process(load)
	begin
		if(load='1') then
			d0<=data0;d1<=data1;d2<=data2;d3<=data3;
			d4<=data4;d5<=data5;d6<=data6;d7<=data7;
		end if;
	end process;
	dout0<=d0;dout1<=d1;dout2<=d2;dout3<=d3;
	dout4<=d4;dout5<=d5;dout6<=d6;dout7<=d7;
end behv;