cnt10.vhd

福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk:	in std_logic;
	clr:	in std_logic;
	ena:	in std_logic;
	cq:	out std_logic_vector(3 downto 0);
	carry_out:	out std_logic);
end cnt10;

architecture behv of cnt10 is
	signal cqi: std_logic_vector(3 downto 0);
begin
	process(clk,clr,ena)
	begin
		if clr='1' then
			cqi<=(others=>'0');
		elsif clk'event and clk='1' then
			if ena='1' then
				if cqi<9 then
					cqi<= cqi+1;
				else
					cqi<=(others=>'0');
				end if;
			end if;
		end if;
	end process;
	process(cqi)
	begin
		if cqi=0 then
			carry_out<='1';
		else
			carry_out<='0';
		end if;
	end process;
	cq<=cqi;
end behv;