crc_send.v

来自「循环冗余校验」· Verilog 代码 · 共 49 行

module crc_send(data_send,
                data_in,
                reset,
                clk,
                ready);
                
 parameter  WIDTH=1,AMOUNT=8;
 
 input [WIDTH-1:0]data_in;
 input reset,clk;
 output ready;
 output [WIDTH*AMOUNT+15:0] data_send;
 reg ready;
 reg [WIDTH*AMOUNT+15:0] data_send;
 reg [WIDTH*AMOUNT+15:0] buf_in;
 reg[3:0] n,i;
 
 always @ (posedge clk or posedge reset)
     begin
       if(reset)
         n=0;
       else
          if(n<AMOUNT-1)
            begin
              ready<=0;
              buf_in=buf_in<<WIDTH;
              buf_in[WIDTH-1:0]=data_in;
              n=n+1;
            end
           else
             begin
               buf_in=buf_in<<WIDTH;
               buf_in[WIDTH-1:0]=data_in;
               buf_in=buf_in<<16;
               data_send=buf_in;
               for(i=0;i<WIDTH*AMOUNT;i=i+1)
                 if(buf_in[WIDTH*AMOUNT+15-i])
                       begin
                              buf_in[WIDTH*AMOUNT+15-i]=~buf_in[WIDTH*AMOUNT+15-i];
                              buf_in[WIDTH*AMOUNT+14-i]=~buf_in[WIDTH*AMOUNT+14-i];
                              buf_in[WIDTH*AMOUNT+1-i]=~buf_in[WIDTH*AMOUNT+1-i];
                              buf_in[WIDTH*AMOUNT-1-i]=~buf_in[WIDTH*AMOUNT-1-i];
                          end
                    data_send[15:0]=buf_in[15:0];
                    n=0;
                    ready<=1;
           end
      end
  endmodule