crc_receive.v

来自「循环冗余校验」· Verilog 代码 · 共 64 行

module crc_receive(data_receive,
                   data_out,
                   resend,
                   clk,
                   ready,
                   err);

parameter WIDTH=1,AMOUNT=8;

output[WIDTH-1:0] data_out;
output  resend;
input [WIDTH*AMOUNT+15:0] data_receive;
input clk,ready,err;
reg [WIDTH-1:0] data_out;
reg resend;
reg [WIDTH*AMOUNT+15:0] buf_receive;
reg right;
reg [3:0] m,j;

always @ (posedge clk)
       begin
         if(ready)
         begin
           buf_receive=data_receive;
            if(err)
               buf_receive[23]=~buf_receive[23];
               for(j=0;j<WIDTH*AMOUNT;j=j+1)
                 if(buf_receive[WIDTH*AMOUNT+15-j])
                       begin
                              buf_receive[WIDTH*AMOUNT+15-j]=~buf_receive[WIDTH*AMOUNT+15-j];
                              buf_receive[WIDTH*AMOUNT+14-j]=~buf_receive[WIDTH*AMOUNT+14-j];
                              buf_receive[WIDTH*AMOUNT+1-j]=~buf_receive[WIDTH*AMOUNT+1-j];
                              buf_receive[WIDTH*AMOUNT-1-j]=~buf_receive[WIDTH*AMOUNT-1-j];
                          end
                     if(!buf_receive)
                        begin
                          right=1;
                          resend=0;
                          buf_receive=data_receive;
                          data_out=buf_receive[WIDTH*AMOUNT+15:WIDTH*AMOUNT+16-WIDTH];
                          buf_receive=buf_receive<<WIDTH;
                          m=1;
                        end
                       else
                         begin
                           right=0;
                           resend=1;
                           data_out='bz;
                         end
             end
             else if(right)
                 begin
                    if(m<AMOUNT)
                     begin
                       data_out=buf_receive[WIDTH*AMOUNT+15:WIDTH*AMOUNT+16-WIDTH]; 
                       buf_receive=buf_receive<<WIDTH;
                       m=m+1;
                     end
                 end
             end
    endmodule