crc_test.v

来自「循环冗余校验」· Verilog 代码 · 共 27 行

module crc_test;
    reg data_in,reset,clk,err;
    reg [15:0] shift;
    wire [23:0] data_send;
    
always #50 clk=~clk;

initial
   begin
       clk=0;
       shift=16'h1247;
       reset=0;
       #10 reset=1;
       #20 reset=0;
       #9600 err=1;
       #100 err=0;
      #5000 $finish;
   end
always @ (posedge clk)
     begin
        data_in=shift[15];
        shift={shift[14:0],shift[15]};
     end
 
   crc_send send(data_send,data_in,reset,clk,ready);
   crc_receive receive(data_send,data_out,resend,clk,ready,err);
   endmodule