_primary.vhd

循环冗余校验

library verilog;
use verilog.vl_types.all;
entity crc_receive is
    generic(
        WIDTH           : integer := 1;
        AMOUNT          : integer := 8
    );
    port(
        data_receive    : in     vl_logic_vector;
        data_out        : out    vl_logic_vector;
        resend          : out    vl_logic;
        clk             : in     vl_logic;
        ready           : in     vl_logic;
        err             : in     vl_logic
    );
end crc_receive;