counter.rpt

来自「Traffic light written with Verilog」· RPT 代码 · 共 1,049 行 · 第 1/4 页

         #  _LC7_F1
         #  _LC8_F1
         #  _LC5_F3;

-- Node name is '~22~2' 
-- Equation name is '~22~2', location is LC1_F10, type is buried.
-- synthesized logic cell 
_LC1_F10 = LCELL( _EQ034);
  _EQ034 =  _LC3_F10
         #  _LC5_F10
         # !_LC6_F10
         #  _LC8_F10;

-- Node name is '~22~3' 
-- Equation name is '~22~3', location is LC4_F8, type is buried.
-- synthesized logic cell 
_LC4_F8  = LCELL( _EQ035);
  _EQ035 = !_LC6_F8
         # !_LC2_F10
         # !_LC7_F8
         #  _LC8_F8;

-- Node name is '~22~4' 
-- Equation name is '~22~4', location is LC2_F3, type is buried.
-- synthesized logic cell 
_LC2_F3  = LCELL( _EQ036);
  _EQ036 =  _LC4_F3
         #  _LC2_F8
         # !_LC7_F3
         #  _LC8_F3;

-- Node name is ':22' 
-- Equation name is '_LC3_F8', type is buried 
!_LC3_F8 = _LC3_F8~NOT;
_LC3_F8~NOT = LCELL( _EQ037);
  _EQ037 =  _LC3_F1
         #  _LC1_F10
         #  _LC4_F8
         #  _LC2_F3;

-- Node name is '~68~1' 
-- Equation name is '~68~1', location is LC6_B29, type is buried.
-- synthesized logic cell 
_LC6_B29 = LCELL( _EQ038);
  _EQ038 =  _LC7_B29
         #  _LC4_B19
         #  _LC4_B29
         #  _LC2_B19;

-- Node name is '~68~2' 
-- Equation name is '~68~2', location is LC7_B24, type is buried.
-- synthesized logic cell 
_LC7_B24 = LCELL( _EQ039);
  _EQ039 = !_LC3_B19
         #  _LC3_B24
         #  _LC2_B24
         #  _LC6_B19;

-- Node name is ':94' 
-- Equation name is '_LC4_B19', type is buried 
_LC4_B19 = LCELL( _EQ040);
  _EQ040 =  first &  _LC2_F1
         # !first &  need_sec7;

-- Node name is ':95' 
-- Equation name is '_LC7_B29', type is buried 
_LC7_B29 = LCELL( _EQ041);
  _EQ041 =  first &  _LC8_B29
         # !first &  need_sec6;

-- Node name is ':96' 
-- Equation name is '_LC4_B29', type is buried 
_LC4_B29 = LCELL( _EQ042);
  _EQ042 =  first &  _LC1_B29
         # !first &  need_sec5;

-- Node name is ':97' 
-- Equation name is '_LC2_B19', type is buried 
_LC2_B19 = LCELL( _EQ043);
  _EQ043 =  first &  _LC5_B19
         # !first &  need_sec4;

-- Node name is ':98' 
-- Equation name is '_LC3_B24', type is buried 
_LC3_B24 = LCELL( _EQ044);
  _EQ044 =  first &  _LC4_B24
         # !first &  need_sec3;

-- Node name is ':99' 
-- Equation name is '_LC6_B19', type is buried 
_LC6_B19 = LCELL( _EQ045);
  _EQ045 =  first &  _LC7_B19
         # !first &  need_sec2;

-- Node name is ':100' 
-- Equation name is '_LC2_B24', type is buried 
_LC2_B24 = LCELL( _EQ046);
  _EQ046 =  first &  _LC6_B24
         # !first &  need_sec1;

-- Node name is ':101' 
-- Equation name is '_LC3_B19', type is buried 
_LC3_B19 = LCELL( _EQ047);
  _EQ047 = !first &  need_sec0
         #  first &  _LC1_B19;

-- Node name is '~126~1' 
-- Equation name is '~126~1', location is LC5_F1, type is buried.
-- synthesized logic cell 
_LC5_F1  = LCELL( _EQ048);
  _EQ048 = !discount & !_LC3_F8;

-- Node name is ':156' 
-- Equation name is '_LC2_F1', type is buried 
_LC2_F1  = DFFE( _EQ049, GLOBAL( clk),  VCC,  VCC, !_LC1_G15);
  _EQ049 =  _LC2_B29 &  _LC4_B19
         # !_LC2_B29 &  _LC3_F8 & !_LC4_B19
         # !_LC3_F8 &  _LC4_B19;

-- Node name is ':157' 
-- Equation name is '_LC8_B29', type is buried 
_LC8_B29 = DFFE( _EQ050, GLOBAL( clk),  VCC,  VCC, !_LC1_G15);
  _EQ050 =  _LC5_B29 &  _LC7_B29
         #  _LC3_F8 & !_LC5_B29 & !_LC7_B29
         # !_LC3_F8 &  _LC7_B29;

-- Node name is ':158' 
-- Equation name is '_LC1_B29', type is buried 
_LC1_B29 = DFFE( _EQ051, GLOBAL( clk),  VCC,  VCC, !_LC1_G15);
  _EQ051 =  _LC3_B29 &  _LC4_B29
         # !_LC3_B29 &  _LC3_F8 & !_LC4_B29
         # !_LC3_F8 &  _LC4_B29;

-- Node name is ':159' 
-- Equation name is '_LC5_B19', type is buried 
_LC5_B19 = DFFE( _EQ052, GLOBAL( clk),  VCC,  VCC, !_LC1_G15);
  _EQ052 =  _LC1_B24 &  _LC2_B19
         # !_LC1_B24 & !_LC2_B19 &  _LC3_F8
         #  _LC2_B19 & !_LC3_F8;

-- Node name is ':160' 
-- Equation name is '_LC4_B24', type is buried 
_LC4_B24 = DFFE( _EQ053, GLOBAL( clk),  VCC,  VCC, !_LC1_G15);
  _EQ053 =  _LC3_B24 &  _LC8_B24
         # !_LC3_B24 &  _LC3_F8 & !_LC8_B24
         #  _LC3_B24 & !_LC3_F8;

-- Node name is ':161' 
-- Equation name is '_LC7_B19', type is buried 
_LC7_B19 = DFFE( _EQ054, GLOBAL( clk),  VCC,  VCC, !_LC1_G15);
  _EQ054 = !_LC3_F8 &  _LC6_B19
         #  _LC6_B19 &  _LC8_B19
         #  _LC3_F8 & !_LC6_B19 & !_LC8_B19;

-- Node name is ':162' 
-- Equation name is '_LC6_B24', type is buried 
_LC6_B24 = DFFE( _EQ055, GLOBAL( clk),  VCC,  VCC, !_LC1_G15);
  _EQ055 =  _LC2_B24 & !_LC3_F8
         #  _LC2_B24 &  _LC3_B19
         # !_LC2_B24 & !_LC3_B19 &  _LC3_F8;

-- Node name is ':163' 
-- Equation name is '_LC1_B19', type is buried 
_LC1_B19 = DFFE( _EQ056, GLOBAL( clk),  VCC,  VCC, !_LC1_G15);
  _EQ056 =  _LC3_B19 & !_LC3_F8
         # !_LC3_B19 &  _LC3_F8;



Project Informationc:\documents and settings\no7\my documents\traffic light\counter.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:02
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:10


Memory Allocated
-----------------

Peak memory allocated during compilation  = 88,862K