counter.rpt
来自「Traffic light written with Verilog」· RPT 代码 · 共 1,049 行 · 第 1/4 页
RPT
1,049 行
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 12/243 ( 4%)
Total logic cells used: 57/2880 ( 1%)
Total embedded cells used: 0/160 ( 0%)
Total EABs used: 0/10 ( 0%)
Average fan-in: 3.28/4 ( 82%)
Total fan-in: 187/11520 ( 1%)
Total input pins required: 10
Total input I/O cell registers required: 0
Total output pins required: 8
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 57
Total flipflops required: 26
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 8/2880 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 8 0 0 0 0 8 0 0 0 0 0 0 0 24/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 8 0 8 0 0 0 0 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 0 8 0 0 0 0 8 0 8 0 0 0 0 1 0 0 0 0 8 0 0 0 0 8 0 0 0 0 8 0 0 0 0 0 0 0 57/0
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\counter.rpt
counter
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
D12 - - - -- INPUT G ^ 0 0 0 0 clk
E12 - - - -- INPUT ^ 0 0 0 3 discount
R12 - - - -- INPUT ^ 0 0 0 1 need_sec0
H11 - - - -- INPUT ^ 0 0 0 1 need_sec1
V11 - - - -- INPUT ^ 0 0 0 1 need_sec2
P11 - - - -- INPUT ^ 0 0 0 1 need_sec3
H3 - - B -- INPUT ^ 0 0 0 1 need_sec4
J16 - - B -- INPUT ^ 0 0 0 1 need_sec5
H5 - - B -- INPUT ^ 0 0 0 1 need_sec6
H4 - - B -- INPUT ^ 0 0 0 1 need_sec7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\counter.rpt
counter
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
G18 - - B -- OUTPUT 0 1 0 0 rest_sec0
H22 - - B -- OUTPUT 0 1 0 0 rest_sec1
H19 - - B -- OUTPUT 0 1 0 0 rest_sec2
F22 - - B -- OUTPUT 0 1 0 0 rest_sec3
H18 - - B -- OUTPUT 0 1 0 0 rest_sec4
J7 - - B -- OUTPUT 0 1 0 0 rest_sec5
J17 - - B -- OUTPUT 0 1 0 0 rest_sec6
W3 - - - 01 OUTPUT 0 1 0 0 rest_sec7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\counter.rpt
counter
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - F 01 AND2 0 3 0 4 |Adder:adder1|lpm_add_sub:73|addcore:adder|:107
- 6 - F 03 AND2 0 2 0 1 |Adder:adder1|lpm_add_sub:73|addcore:adder|:111
- 3 - F 03 AND2 0 4 0 2 |Adder:adder1|lpm_add_sub:73|addcore:adder|:119
- 1 - F 03 AND2 0 2 0 3 |Adder:adder1|lpm_add_sub:73|addcore:adder|:123
- 5 - F 08 AND2 0 3 0 3 |Adder:adder1|lpm_add_sub:73|addcore:adder|:131
- 1 - F 08 AND2 0 3 0 4 |Adder:adder1|lpm_add_sub:73|addcore:adder|:139
- 7 - F 10 AND2 0 2 0 1 |Adder:adder1|lpm_add_sub:73|addcore:adder|:143
- 4 - F 10 AND2 0 4 0 2 |Adder:adder1|lpm_add_sub:73|addcore:adder|:151
- 5 - F 10 DFFE + 0 3 0 1 |Adder:adder1|:57
- 6 - F 10 DFFE + 0 2 0 2 |Adder:adder1|:58
- 8 - F 10 DFFE + 0 3 0 2 |Adder:adder1|:59
- 3 - F 10 DFFE + 0 3 0 3 |Adder:adder1|:60
- 2 - F 10 DFFE + 0 2 0 4 |Adder:adder1|:61
- 6 - F 08 DFFE + 0 3 0 2 |Adder:adder1|:62
- 7 - F 08 DFFE + 0 2 0 3 |Adder:adder1|:63
- 8 - F 08 DFFE + 0 3 0 2 |Adder:adder1|:64
- 2 - F 08 DFFE + 0 2 0 3 |Adder:adder1|:65
- 4 - F 03 DFFE + 0 2 0 2 |Adder:adder1|:66
- 7 - F 03 DFFE + 0 3 0 2 |Adder:adder1|:67
- 8 - F 03 DFFE + 0 3 0 3 |Adder:adder1|:68
- 5 - F 03 DFFE + 0 2 0 4 |Adder:adder1|:69
- 8 - F 01 DFFE + 0 3 0 2 |Adder:adder1|:70
- 7 - F 01 DFFE + 0 2 0 3 |Adder:adder1|:71
- 6 - F 01 DFFE + 0 1 0 4 |Adder:adder1|:72
- 1 - G 15 SOFT s ! 1 0 0 8 discount~1
- 8 - B 19 OR2 0 2 0 1 |lpm_add_sub:172|addcore:adder|pcarry1
- 8 - B 24 OR2 0 3 0 1 |lpm_add_sub:172|addcore:adder|pcarry2
- 1 - B 24 OR2 0 4 0 2 |lpm_add_sub:172|addcore:adder|pcarry3
- 3 - B 29 OR2 0 2 0 2 |lpm_add_sub:172|addcore:adder|pcarry4
- 5 - B 29 OR2 0 2 0 2 |lpm_add_sub:172|addcore:adder|pcarry5
- 2 - B 29 OR2 0 2 0 2 |lpm_add_sub:172|addcore:adder|pcarry6
- 3 - F 01 OR2 s 0 4 0 1 ~22~1
- 1 - F 10 OR2 s 0 4 0 1 ~22~2
- 4 - F 08 OR2 s 0 4 0 1 ~22~3
- 2 - F 03 OR2 s 0 4 0 1 ~22~4
- 3 - F 08 OR2 ! 0 4 0 10 :22
- 6 - B 29 OR2 s 0 4 0 1 ~68~1
- 7 - B 24 OR2 s 0 4 0 1 ~68~2
- 5 - B 24 DFFE + 1 3 0 8 first (:73)
- 4 - B 19 OR2 1 2 0 3 :94
- 7 - B 29 OR2 1 2 0 3 :95
- 4 - B 29 OR2 1 2 0 3 :96
- 2 - B 19 OR2 1 2 0 3 :97
- 3 - B 24 OR2 1 2 0 3 :98
- 6 - B 19 OR2 1 2 0 4 :99
- 2 - B 24 OR2 1 2 0 5 :100
- 3 - B 19 OR2 1 2 0 6 :101
- 5 - F 01 AND2 s 1 1 0 1 ~126~1
- 4 - F 01 DFFE + 0 3 0 16 enable (:129)
- 2 - F 01 DFFE + 0 4 1 1 :156
- 8 - B 29 DFFE + 0 4 1 1 :157
- 1 - B 29 DFFE + 0 4 1 1 :158
- 5 - B 19 DFFE + 0 4 1 1 :159
- 4 - B 24 DFFE + 0 4 1 1 :160
- 7 - B 19 DFFE + 0 4 1 1 :161
- 6 - B 24 DFFE + 0 4 1 1 :162
- 1 - B 19 DFFE + 0 3 1 1 :163
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\counter.rpt
counter
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 9/144( 6%) 0/ 72( 0%) 14/ 72( 19%) 4/16( 25%) 7/16( 43%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 2/144( 1%) 12/ 72( 16%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\documents and settings\no7\my documents\traffic light\counter.rpt
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