conv_code.vhd

用VHDL实现卷积码编码

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTIT  conv_code IS
PORT(
        clk,indata,clm      :      IN    STD_LOGIC;
outl,out2,oclk_2           :    OUT    STD_LOGIC;
code_out                   :   OUT  STD_LOGIC
);
END conv_code;
ARCHITECTURE shift OF conv_code IS
COMPONENT frediv
PORT(
clk ,clm                   :   IN    STD_LOGIC;   
clk_div2                   : OUT    STD_LOGIC
 );
END COMPONENT;
SIGNAL d4                :       STD_LOGIC_VECTOR(0to3);
SIGNAL outdata1,outdata2,outdata:STD_LOGIC;
SIGNAL clk_2              :      STD_LOGIC;
BEGIN
u0:frediv PORT MAP
(clk=>clk,clm=>clm,clk_div2=>clk_2) ;
d4(0)<=indata;
PROCESS(clk_2)
BEGIN
IF  (clk_2'event  AND clk_2 ='1')THEN
d4(1)<= d4(0);
d4(2)<=d4(1);
d4(3)<=d4(2);
outdatal <= d4(0) xor d4(1) XOR d4(2) XOR d4(3);
outdata2 <= d4(0) xor d4(l) XOR d4(3);
END IF ;
END PROCESS;
out data<=outdatal when clk_2 = '1'else
out data2 when clk_2= '0 'else
'0';
PROCESS(clk)
BEGIN
IF( clk'event AND clk= '1')THEN
code_out <= outdata;
END IF ;
END PROCESS;
out1<=outdatal;
out2<=outdata2;
oclk_2 <=clk_2;
END shift;