test.tan.summary

uart 通用异步接受机 编译环境为quartus

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.800 ns
From           : RESET
To             : uart:inst1|rxdatardy
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 4.000 ns
From           : uart:inst|txdatardy
To             : txdry
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 6.400 ns
From           : RD
To             : DATA_OUT[0]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 5.300 ns
From           : RX
To             : uart:inst|rxstop
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 76.34 MHz ( period = 13.100 ns )
From           : uart:inst1|rxidle
To             : uart:inst1|hunt
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : uart:inst|txdatardy
To             : uart:inst|tx
From Clock     : clk
To Clock       : clk
Failed Paths   : 12

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 12

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