synth_pack.vhd

一个8051的VHDL代码

--
-- VHDL Package Header mc8051.synth_pack
--
-- Created:
--          by - mrmayer.UNKNOWN (eeultra11.ee.umr.edu)
--          at - 11:10:46 03/18/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.0 (Build 110)
--
------------------------------------------------------------------------------
-- Model        :   8051 Behavioral Model,
--                  Supporting Package of Procedures
--
-- Author       :   Michael Mayer,
--                  Department of Electrical Engineering
--                  University of Missouri - Rolla
--
-- Derived from :   Sundar Subbarayan
--                  UC Riverside CS 122a (lab 3)
--                  Professor: Dr.Frank Vahid
--                  17th January 1996
--
-- Date Started :   September 15, 1997
--
-- Limitations  :
--
-- Revisions    :
--
-- REV    DATE     Description
-- -----  --------   _____________________________________
-- 2.0    11/04/97   Initial implementation of types for
--                   memory, functions or, and, xor, not
--                   and procedure load_program
--
-- 2.1    11/12/97   Changed memory to lo and hi mem's
--
-- 2.2    11/13/97   Added type for states for machine cycles
--
--
------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

package synth_pack is
   SUBTYPE bvec       IS UNSIGNED(7 DOWNTO 0);
   SUBTYPE wvec       IS UNSIGNED(15 DOWNTO 0);
 
   -- The following type is used to declare if direct or indirect memory
   -- access is being used and, hence, which segment of upper memory
   -- is to be used.
   TYPE    access_type IS (direct, indirect);
 
   -- The following type is used to break up the machine cycle
   -- into 6 states, with 2 pulses for each state
   CONSTANT s1p1 : std_logic_vector(3 DOWNTO 0) := "0100"; 
   CONSTANT s1p2 : std_logic_vector(3 DOWNTO 0) := "0101"; 
   CONSTANT s2p1 : std_logic_vector(3 DOWNTO 0) := "0110"; 
   CONSTANT s2p2 : std_logic_vector(3 DOWNTO 0) := "0111"; 
   CONSTANT s3p1 : std_logic_vector(3 DOWNTO 0) := "1000"; 
   CONSTANT s3p2 : std_logic_vector(3 DOWNTO 0) := "1001"; 
   CONSTANT s4p1 : std_logic_vector(3 DOWNTO 0) := "1010"; 
   CONSTANT s4p2 : std_logic_vector(3 DOWNTO 0) := "1011"; 
   CONSTANT s5p1 : std_logic_vector(3 DOWNTO 0) := "1100"; 
   CONSTANT s5p2 : std_logic_vector(3 DOWNTO 0) := "1101"; 
   CONSTANT s6p1 : std_logic_vector(3 DOWNTO 0) := "1110"; 
   CONSTANT s6p2 : std_logic_vector(3 DOWNTO 0) := "1111"; 
 
   FUNCTION to_high_imped(arg : bvec) RETURN bvec;
 
end synth_pack;