hi_dmem_spec.vhd

一个8051的VHDL代码

--------------------------------------------------
-- Model        :   8051 Behavioral Model,
--                  VHDL Entity mc8051.hi_dmem.interface
--
-- Author       :   Michael Mayer ([e-mail]),
--                  Dr. Hardy J. Pottinger,
--                  Department of Electrical Engineering
--                  University of Missouri - Rolla
--
-- Created at   :   09/22/98 19:32:45
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.synth_pack.all;

ENTITY hi_dmem IS
   PORT( 
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 )  ;
      indirect_sel : IN     std_logic ;
      int_clk : IN     std_logic ;
      int_rst : IN     std_logic ;
      rd_gb : IN     std_logic ;
      wr_gb : IN     std_logic ;
      acknow : OUT    std_logic ;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 ) 
   );

-- Declarations

END hi_dmem ;
--
-- VHDL Architecture mc8051.hi_dmem.spec
--
-- Created:
--          by - mrmayer.UNKNOWN (eeultra20.ee.umr.edu)
--          at - 22:31:08 03/29/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.0 (Build 110)
--
architecture spec of hi_dmem is

    CONSTANT low_address : natural := 0;
    CONSTANT high_address: natural := 127;
    CONSTANT addr_width  : natural := 7;
    CONSTANT width       : natural := 8;
    SIGNAL do_write, do_read : std_logic;   -- flags to command the memory 
        -- to perform a given action (rising edge sensitive)
    SIGNAL read_data : std_logic_vector(width-1 DOWNTO 0);  -- the data read 
 
BEGIN
 
    do_write <= '1' WHEN (addr_gb(7)='1' AND indirect_sel = '1') AND wr_gb='1'
                ELSE '0';
    do_read  <= '1' WHEN (addr_gb(7)='1' AND indirect_sel = '1') AND rd_gb='1'
                ELSE '0';
    data_gb <= read_data WHEN do_read='1' ELSE (OTHERS => 'Z');

    memory: PROCESS (do_write, do_read) IS
 
 
    TYPE memory_array IS
    ARRAY (natural RANGE low_address TO high_address) OF std_logic_vector(width-
1  DOWNTO 0);
 
    VARIABLE mem: memory_array;
    VARIABLE address : natural;
 
    VARIABLE write_data: std_logic_vector(width-1 DOWNTO 0);
    BEGIN
        address := TO_INTEGER(unsigned(addr_gb(6 DOWNTO 0)));
        IF rising_edge(do_write) THEN
            mem(address) := to_X01(data_gb);
        ELSIF rising_edge(do_read) THEN
            read_data <= mem(address);
        END IF;
    END PROCESS memory;

end spec;