simtut_tb.vhd

这些是verilog编程实例2,仅供参考

--  J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\SIMTUT_TB.VHD
--  VHDL testbench created by 
--  Xilinx's StateBench 1.01
--  Sat Oct 26 14:36:48 2002

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY synopsys;
USE synopsys.attributes.all;

LIBRARY ieee;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS
FILE RESULTS: TEXT IS OUT "results.txt";
	COMPONENT SIMTUT
		PORT (ac : OUT std_logic_vector (3 DOWNTO 0);
			CLK,cyc,di,RESET: IN std_logic;
			rc : OUT std_logic);
	END COMPONENT;

	SIGNAL ac : std_logic_vector (3 DOWNTO 0) := std_logic_vector'("0000");
	SIGNAL CLK,cyc,di,RESET: std_logic := '0';
	SIGNAL rc : std_logic := '0';

	BEGIN

	UUT : SIMTUT PORT MAP (
		ac=>ac,
		CLK=>CLK,
		cyc=>cyc,
		di=>di,
		RESET=>RESET,
		rc=>rc);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_ac(
			next_ac : std_logic_vector (3 DOWNTO 0)
		) IS BEGIN
			IF (ac /= next_ac) THEN 
				write(TX_OUT,string'(
					"* Error, ac="));
				write(TX_OUT, ac);
				write(TX_OUT, string'(" Expected = "));
				write(TX_OUT, next_ac);
				write(TX_OUT, string'(" *"));
				writeline(results, TX_OUT);
				TX_ERROR := TX_ERROR + 1;
			END IF;
			ASSERT (ac=next_ac) REPORT
				 "Error, ac has incorrect value"
				 SEVERITY ERROR;
		END;

		PROCEDURE CHECK_rc(
			next_rc : std_logic
		) IS BEGIN
			IF (rc /= next_rc) THEN 
				write(TX_OUT,string'(
					"* Error, rc="));
				write(TX_OUT, rc);
				write(TX_OUT, string'(" Expected = "));
				write(TX_OUT, next_rc);
				write(TX_OUT, string'(" *"));
				writeline(results, TX_OUT);
				TX_ERROR := TX_ERROR + 1;
			END IF;
			ASSERT (rc=next_rc) REPORT
				 "Error, rc has incorrect value"
				 SEVERITY ERROR;
		END;

		BEGIN
		-- --------------------
		CLK <= '0'; -- Initialize clock inactive
		cyc <= '0';
		di <= '0';
		RESET <= '1';
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 0 Time 15 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0000"));
		CHECK_rc('1');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		RESET <= '0';
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 1 Time 115 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0000"));
		CHECK_rc('1');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		cyc <= '1';
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 2 Time 215 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0000"));
		CHECK_rc('0');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 3 Time 315 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0000"));
		CHECK_rc('0');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		cyc <= '0';
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 4 Time 415 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0000"));
		CHECK_rc('0');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 5 Time 515 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0000"));
		CHECK_rc('0');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 6 Time 615 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0000"));
		CHECK_rc('0');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 7 Time 715 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0000"));
		CHECK_rc('0');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		cyc <= '1';
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 8 Time 815 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0000"));
		CHECK_rc('0');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		cyc <= '0';
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 9 Time 915 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0000"));
		CHECK_rc('0');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		di <= '1';
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 10 Time 1015 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0000"));
		CHECK_rc('0');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 11 Time 1115 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0001"));
		CHECK_rc('0');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;
		WAIT FOR 15 ns;
		-- ----------------------
		CLK <= '1'; -- Clock 12 Time 1215 ns
		WAIT FOR 20 ns;
		CHECK_ac(std_logic_vector'("0001"));
		CHECK_rc('1');
		WAIT FOR 30 ns;
		CLK <= '0'; -- inactive clock edge
		WAIT FOR 35 ns;

		IF (TX_ERROR = 0) THEN 
			write(TX_OUT,string'("No errors or warnings"));
			writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful.  No problems detected."
				SEVERITY FAILURE;
		ELSE
			write(TX_OUT, TX_ERROR);
			write(TX_OUT, string'(
				" errors found in simulation"));
			writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION SIMTUT_cfg OF testbench IS
	FOR testbench_arch
	END FOR;
END SIMTUT_cfg;