tut.vhd

这些是verilog编程实例2,仅供参考

--  J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\TUT.vhd
--  VHDL code created by Xilinx's StateCAD 5.03
--  Sat Oct 26 10:39:04 2002

--  This VHDL code (for use with IEEE compliant tools) was generated using: 
--  enumerated state assignment with structured code format.
--  Minimization is enabled,  implied else is enabled, 
--  and outputs are speed optimized.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY ieee;
USE ieee.std_logic_unsigned.all;

ENTITY SHELL_TUT IS
	PORT (CLK,cyc,di,RESET: IN std_logic;
		ac0,ac1,ac2,ac3 : OUT std_logic);

	SIGNAL BP_ac0,BP_ac1,BP_ac2,BP_ac3,cnt0,cnt1,rc,s0,s1,s2,s3: std_logic;
END;

ARCHITECTURE BEHAVIOR OF SHELL_TUT IS
	TYPE type_sreg IS (Add,Get_1,Get_2,Idle,Split);
	SIGNAL sreg, next_sreg : type_sreg;
	SIGNAL next_BP_ac0,next_BP_ac1,next_BP_ac2,next_BP_ac3,next_cnt0,next_cnt1,
		next_rc,next_s0,next_s1,next_s2,next_s3 : std_logic;
	SIGNAL ac : std_logic_vector (3 DOWNTO 0);
	SIGNAL BP_ac : std_logic_vector (3 DOWNTO 0);
	SIGNAL cnt : std_logic_vector (1 DOWNTO 0);
	SIGNAL s : std_logic_vector (3 DOWNTO 0);
BEGIN
	PROCESS (CLK, rc)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF (rc='1') THEN
				cnt1 <= '0';
			ELSE
				cnt1 <= next_cnt1;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (CLK, rc)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF (rc='1') THEN
				cnt0 <= '0';
			ELSE
				cnt0 <= next_cnt0;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (CLK)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF ( RESET='1' ) THEN
				sreg <= Idle;
			ELSE
				sreg <= next_sreg;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (CLK)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF ( RESET='1' ) THEN
				BP_ac3 <= '0';
			ELSE
				BP_ac3 <= next_BP_ac3;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (CLK)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF ( RESET='1' ) THEN
				BP_ac2 <= '0';
			ELSE
				BP_ac2 <= next_BP_ac2;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (CLK)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF ( RESET='1' ) THEN
				BP_ac1 <= '0';
			ELSE
				BP_ac1 <= next_BP_ac1;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (CLK)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF ( RESET='1' ) THEN
				BP_ac0 <= '0';
			ELSE
				BP_ac0 <= next_BP_ac0;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (CLK)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF ( RESET='1' ) THEN
				s3 <= '0';
			ELSE
				s3 <= next_s3;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (CLK)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF ( RESET='1' ) THEN
				s2 <= '0';
			ELSE
				s2 <= next_s2;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (CLK)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF ( RESET='1' ) THEN
				s1 <= '0';
			ELSE
				s1 <= next_s1;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (CLK)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF ( RESET='1' ) THEN
				s0 <= '0';
			ELSE
				s0 <= next_s0;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (CLK)
	BEGIN
		IF CLK='1' AND CLK'event THEN
			IF ( RESET='1' ) THEN
				rc <= '1';
			ELSE
				rc <= next_rc;
			END IF;
		END IF;
	END PROCESS;

	PROCESS (sreg,BP_ac0,BP_ac1,BP_ac2,BP_ac3,cnt0,cnt1,cyc,di,rc,RESET,s0,s1,s2
		,s3,BP_ac,s)
	BEGIN
		next_BP_ac0 <= BP_ac0;next_BP_ac1 <= BP_ac1;next_BP_ac2 <= BP_ac2;
			next_BP_ac3 <= BP_ac3;next_rc <= rc;next_s0 <= s0;next_s1 <= s1;next_s2 <= 
			s2;next_s3 <= s3;

		BP_ac <= (( std_logic_vector'(BP_ac3, BP_ac2, BP_ac1, BP_ac0)));
		s <= (( std_logic_vector'(s3, s2, s1, s0)));


		next_sreg<=Add;

		IF ( RESET='1' ) THEN
			next_sreg<=Idle;
			next_rc<='1';

			s <= (std_logic_vector'("0000"));
			BP_ac <= (std_logic_vector'("0000"));
		ELSE
			CASE sreg IS
				WHEN Add =>
					next_sreg<=Idle;
					next_rc<='1';

					s <= (( std_logic_vector'(s3, s2, s1, s0)));
					BP_ac <= (( std_logic_vector'(BP_ac3, BP_ac2, BP_ac1, BP_ac0)));
				WHEN Get_1 =>
					IF ( cnt0='1' AND cnt1='1' ) THEN
						next_sreg<=Split;

						IF (( rc='1' )) THEN next_rc<='1';
						ELSE next_rc<='0';
						END IF;

						s <= (( std_logic_vector'(s3, s2, s1, s0)));
						BP_ac <= (( std_logic_vector'(BP_ac3, BP_ac2, BP_ac1, BP_ac0)));
					 ELSE
						next_sreg<=Get_1;
						next_rc<='0';

						BP_ac <= (( std_logic_vector'(BP_ac3, BP_ac2, BP_ac1, BP_ac0)));
						s <= (( std_logic_vector'(s2, s1, s0, di)));
					END IF;
				WHEN Get_2 =>
					IF ( cnt0='0' AND cnt1='0' ) THEN
						next_sreg<=Add;

						IF (( rc='1' )) THEN next_rc<='1';
						ELSE next_rc<='0';
						END IF;

						s <= (( std_logic_vector'(s3, s2, s1, s0)));
						BP_ac <= ( (( std_logic_vector'(BP_ac3, BP_ac2, BP_ac1, BP_ac0)) +( 
							std_logic_vector'(s3, s2, s1, s0)) ));
					 ELSE
						next_sreg<=Get_2;

						IF (( rc='1' )) THEN next_rc<='1';
						ELSE next_rc<='0';
						END IF;

						BP_ac <= (( std_logic_vector'(BP_ac3, BP_ac2, BP_ac1, BP_ac0)));
						s <= (( std_logic_vector'(s2, s1, s0, di)));
					END IF;
				WHEN Idle =>
					IF ( cyc='1' ) THEN
						next_sreg<=Get_1;
						next_rc<='0';

						BP_ac <= (( std_logic_vector'(BP_ac3, BP_ac2, BP_ac1, BP_ac0)));
						s <= (( std_logic_vector'(s2, s1, s0, di)));
					 ELSE
						next_sreg<=Idle;
						next_rc<='1';

						s <= (( std_logic_vector'(s3, s2, s1, s0)));
						BP_ac <= (( std_logic_vector'(BP_ac3, BP_ac2, BP_ac1, BP_ac0)));
					END IF;
				WHEN Split =>
					next_sreg<=Get_2;

					IF (( rc='1' )) THEN next_rc<='1';
					ELSE next_rc<='0';
					END IF;

					BP_ac <= (( std_logic_vector'(BP_ac3, BP_ac2, BP_ac1, BP_ac0)));
					s <= (( std_logic_vector'(s2, s1, s0, di)));
				WHEN OTHERS =>
			END CASE;
		END IF;

		next_BP_ac3 <= BP_ac(3);
		next_BP_ac2 <= BP_ac(2);
		next_BP_ac1 <= BP_ac(1);
		next_BP_ac0 <= BP_ac(0);
		next_s3 <= s(3);
		next_s2 <= s(2);
		next_s1 <= s(1);
		next_s0 <= s(0);
	END PROCESS;

	PROCESS (cnt0,cnt1,cnt)
	BEGIN
		cnt <= (( std_logic_vector'(cnt1, cnt0)) +std_logic_vector'("01"));
		next_cnt0 <= cnt(0);
		next_cnt1 <= cnt(1);
	END PROCESS;

	PROCESS (BP_ac0,BP_ac1,BP_ac2,BP_ac3,ac)
	BEGIN
		ac <= (( std_logic_vector'(BP_ac3, BP_ac2, BP_ac1, BP_ac0)));
		ac0 <= ac(0);
		ac1 <= ac(1);
		ac2 <= ac(2);
		ac3 <= ac(3);
	END PROCESS;
END BEHAVIOR;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY ieee;
USE ieee.std_logic_unsigned.all;

ENTITY TUT IS
	PORT (ac : OUT std_logic_vector (3 DOWNTO 0);
		CLK,cyc,di,RESET: IN std_logic);
END;

ARCHITECTURE BEHAVIOR OF TUT IS
	COMPONENT SHELL_TUT
		PORT (CLK,cyc,di,RESET: IN std_logic;
			ac0,ac1,ac2,ac3 : OUT std_logic);
	END COMPONENT;
BEGIN
	SHELL1_TUT : SHELL_TUT PORT MAP (CLK=>CLK,cyc=>cyc,di=>di,RESET=>RESET,ac0=>
		ac(0),ac1=>ac(1),ac2=>ac(2),ac3=>ac(3));
END BEHAVIOR;
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