simtut_tb.reg

这些是verilog编程实例2,仅供参考

|  J:\PROJECTS\ISE\SECTION2\STATECAD_DEMO\SIMTUT_TB.REG 
|  StateBench(tm) regression file created by 
|  Xilinx's StateBench 1.01 
|  Sat Oct 26 14:36:48 2002 


restart
constraint set
time_scale ns
time_active 50
time_inactive 50
time_setup 15
time_check 20
powerup_to 0
constraint use
radix decimal
l cyc
l di
h RESET
update
sim 15
|-----------------------
| Clock: 0  Time: 15 ns
sim 20
checka ac 0
checka cnt 1
checka rc 1
checka s 0
sim 30
sim 35
l RESET
update
sim 15
|-----------------------
| Clock: 1  Time: 115 ns
sim 20
checka ac 0
checka cnt 0
checka rc 1
checka s 0
sim 30
sim 35
h cyc
update
sim 15
|-----------------------
| Clock: 2  Time: 215 ns
sim 20
checka ac 0
checka cnt 0
checka rc 0
checka s 0
sim 30
sim 35
sim 15
|-----------------------
| Clock: 3  Time: 315 ns
sim 20
checka ac 0
checka cnt 1
checka rc 0
checka s 0
sim 30
sim 35
l cyc
update
sim 15
|-----------------------
| Clock: 4  Time: 415 ns
sim 20
checka ac 0
checka cnt 2
checka rc 0
checka s 0
sim 30
sim 35
sim 15
|-----------------------
| Clock: 5  Time: 515 ns
sim 20
checka ac 0
checka cnt 3
checka rc 0
checka s 0
sim 30
sim 35
sim 15
|-----------------------
| Clock: 6  Time: 615 ns
sim 20
checka ac 0
checka cnt 0
checka rc 0
checka s 0
sim 30
sim 35
sim 15
|-----------------------
| Clock: 7  Time: 715 ns
sim 20
checka ac 0
checka cnt 1
checka rc 0
checka s 0
sim 30
sim 35
h cyc
update
sim 15
|-----------------------
| Clock: 8  Time: 815 ns
sim 20
checka ac 0
checka cnt 2
checka rc 0
checka s 0
sim 30
sim 35
l cyc
update
sim 15
|-----------------------
| Clock: 9  Time: 915 ns
sim 20
checka ac 0
checka cnt 3
checka rc 0
checka s 0
sim 30
sim 35
h di
update
sim 15
|-----------------------
| Clock: 10  Time: 1015 ns
sim 20
checka ac 0
checka cnt 0
checka rc 0
checka s 1
sim 30
sim 35
sim 15
|-----------------------
| Clock: 11  Time: 1115 ns
sim 20
checka ac 1
checka cnt 1
checka rc 0
checka s 1
sim 30
sim 35
sim 15
|-----------------------
| Clock: 12  Time: 1215 ns
sim 20
checka ac 1
checka cnt 2
checka rc 1
checka s 1
sim 30
sim 35